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GPS Device
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Memory-mapped register structures for the NVIC. More...

Classes | |
| struct | NVIC_ISER_REGDEF_ts |
| NVIC Interrupt Set-Enable Registers (NVIC_ISER). More... | |
| struct | NVIC_ICER_REGDEF_ts |
| NVIC Interrupt Clear-Enable Registers (NVIC_ICER). More... | |
| struct | NVIC_ISPR_REGDEF_ts |
| NVIC Interrupt Set-Pending Registers (NVIC_ISPR). More... | |
| struct | NVIC_ICPR_REGDEF_ts |
| NVIC Interrupt Clear-Pending Registers (NVIC_ICPR). More... | |
| struct | NVIC_IABR_REGDEF_ts |
| NVIC Interrupt Active Bit Registers (NVIC_IABR). More... | |
| struct | NVIC_IPR_REGDEF_ts |
| NVIC Interrupt Priority Registers (NVIC_IPR). More... | |
| struct | NVIC_STIR_REGDEF_ts |
| NVIC Software Trigger Interrupt Register (NVIC_STIR). More... | |
Macros | |
| #define | NVIC_ISER ((NVIC_ISER_REGDEF_ts*)ADDR_NVIC_ISER) |
| #define | NVIC_ICER ((NVIC_ICER_REGDEF_ts*)ADDR_NVIC_ICER) |
| #define | NVIC_ISPR ((NVIC_ISPR_REGDEF_ts*)ADDR_NVIC_ISPR) |
| #define | NVIC_ICPR ((NVIC_ICPR_REGDEF_ts*)ADDR_NVIC_ICPR) |
| #define | NVIC_IABR ((NVIC_IABR_REGDEF_ts*)ADDR_NVIC_IABR) |
| #define | NVIC_IPR ((NVIC_IPR_REGDEF_ts*)ADDR_NVIC_IPR) |
| #define | NVIC_STIR ((NVIC_STIR_REGDEF_ts*)ADDR_NVIC_STIR) |
Memory-mapped register structures for the NVIC.
| #define NVIC_ISER ((NVIC_ISER_REGDEF_ts*)ADDR_NVIC_ISER) |
Definition at line 66 of file arm_cortex_m4.h.
| #define NVIC_ICER ((NVIC_ICER_REGDEF_ts*)ADDR_NVIC_ICER) |
Definition at line 77 of file arm_cortex_m4.h.
| #define NVIC_ISPR ((NVIC_ISPR_REGDEF_ts*)ADDR_NVIC_ISPR) |
Definition at line 88 of file arm_cortex_m4.h.
| #define NVIC_ICPR ((NVIC_ICPR_REGDEF_ts*)ADDR_NVIC_ICPR) |
Definition at line 99 of file arm_cortex_m4.h.
| #define NVIC_IABR ((NVIC_IABR_REGDEF_ts*)ADDR_NVIC_IABR) |
Definition at line 111 of file arm_cortex_m4.h.
| #define NVIC_IPR ((NVIC_IPR_REGDEF_ts*)ADDR_NVIC_IPR) |
Definition at line 124 of file arm_cortex_m4.h.
| #define NVIC_STIR ((NVIC_STIR_REGDEF_ts*)ADDR_NVIC_STIR) |
Definition at line 137 of file arm_cortex_m4.h.