NVIC Interrupt Set-Enable Registers (NVIC_ISER). More...

Public Attributes
uint32_t volatile	NVIC_ISER_ [8]

Detailed Description

NVIC Interrupt Set-Enable Registers (NVIC_ISER).

Writing 1 to a bit enables the corresponding interrupt. Writing 0 has no effect. Eight 32-bit registers cover up to 256 external interrupt lines.

Definition at line 63 of file arm_cortex_m4.h.

Member Data Documentation

uint32_t volatile NVIC_ISER_REGDEF_ts::NVIC_ISER_[8]

ISER[0]–ISER[7]: each bit enables one interrupt line.

Definition at line 64 of file arm_cortex_m4.h.

The documentation for this struct was generated from the following file: