NVIC Interrupt Priority Registers (NVIC_IPR). More...

#include <arm_cortex_m4.h>

Public Attributes
uint32_t volatile	NVIC_IPR_ [60]

Detailed Description

NVIC Interrupt Priority Registers (NVIC_IPR).

Each byte sets the priority of one interrupt. On the Cortex-M4 only the upper bits of each priority byte are implemented (implementation-defined width). 60 registers cover up to 240 external interrupt lines (4 per register).

Definition at line 121 of file arm_cortex_m4.h.

Member Data Documentation

◆ NVIC_IPR_

uint32_t volatile NVIC_IPR_REGDEF_ts::NVIC_IPR_[60]

IPR[0]–IPR[59]: 4 interrupt priorities per register.

Definition at line 122 of file arm_cortex_m4.h.

The documentation for this struct was generated from the following file:

drivers/inc/arm_cortex_m4.h

Public Attributes

Detailed Description

Member Data Documentation

◆ NVIC_IPR_