Fixed memory-mapped base addresses for Cortex-M4 core peripherals. More...
Macros | |
| #define | ADDR_NVIC_ISER (0xE000E100U) |
| #define | ADDR_NVIC_ICER (0xE000E180U) |
| #define | ADDR_NVIC_ISPR (0xE000E200U) |
| #define | ADDR_NVIC_ICPR (0xE000E280U) |
| #define | ADDR_NVIC_IABR (0xE000E300U) |
| #define | ADDR_NVIC_IPR (0xE000E400U) |
| #define | ADDR_NVIC_STIR (0xE000EF00U) |
| #define | ADDR_SYSTICK (0xE000E010U) |
Detailed Description
Fixed memory-mapped base addresses for Cortex-M4 core peripherals.
Macro Definition Documentation
◆ ADDR_NVIC_ISER
| #define ADDR_NVIC_ISER (0xE000E100U) |
NVIC Interrupt Set-Enable Registers base address.
Definition at line 39 of file arm_cortex_m4.h.
◆ ADDR_NVIC_ICER
| #define ADDR_NVIC_ICER (0xE000E180U) |
NVIC Interrupt Clear-Enable Registers base address.
Definition at line 40 of file arm_cortex_m4.h.
◆ ADDR_NVIC_ISPR
| #define ADDR_NVIC_ISPR (0xE000E200U) |
NVIC Interrupt Set-Pending Registers base address.
Definition at line 41 of file arm_cortex_m4.h.
◆ ADDR_NVIC_ICPR
| #define ADDR_NVIC_ICPR (0xE000E280U) |
NVIC Interrupt Clear-Pending Registers base address.
Definition at line 42 of file arm_cortex_m4.h.
◆ ADDR_NVIC_IABR
| #define ADDR_NVIC_IABR (0xE000E300U) |
NVIC Interrupt Active Bit Registers base address.
Definition at line 43 of file arm_cortex_m4.h.
◆ ADDR_NVIC_IPR
| #define ADDR_NVIC_IPR (0xE000E400U) |
NVIC Interrupt Priority Registers base address.
Definition at line 44 of file arm_cortex_m4.h.
◆ ADDR_NVIC_STIR
| #define ADDR_NVIC_STIR (0xE000EF00U) |
NVIC Software Trigger Interrupt Register address.
Definition at line 45 of file arm_cortex_m4.h.
◆ ADDR_SYSTICK
| #define ADDR_SYSTICK (0xE000E010U) |
SysTick control registers base address.
Definition at line 46 of file arm_cortex_m4.h.
