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ssd1309.h
Go to the documentation of this file.
1
40
46
47#ifndef SSD1309_H__
48#define SSD1309_H__
49
50#include "stm32f401re.h"
51#include "stm32f401re_gpio.h"
52#include "err.h"
53
60
61#define SSD1309_WIDTH 128
62#define SSD1309_HEIGHT 64
63#define SSD1309_CHAR_WIDTH 8
64#define SSD1309_CHAR_HEIGHT 8
65#define SSD1309_MAX_CHARS_IN_LINE 16
66
68
75
81typedef enum {
82 SSD1309_LOW_COL_START_ADDR_PAM_0,
83 SSD1309_LOW_COL_START_ADDR_PAM_1,
84 SSD1309_LOW_COL_START_ADDR_PAM_2,
85 SSD1309_LOW_COL_START_ADDR_PAM_3,
86 SSD1309_LOW_COL_START_ADDR_PAM_4,
87 SSD1309_LOW_COL_START_ADDR_PAM_5,
88 SSD1309_LOW_COL_START_ADDR_PAM_6,
89 SSD1309_LOW_COL_START_ADDR_PAM_7,
90 SSD1309_LOW_COL_START_ADDR_PAM_8,
91 SSD1309_LOW_COL_START_ADDR_PAM_9,
92 SSD1309_LOW_COL_START_ADDR_PAM_10,
93 SSD1309_LOW_COL_START_ADDR_PAM_11,
94 SSD1309_LOW_COL_START_ADDR_PAM_12,
95 SSD1309_LOW_COL_START_ADDR_PAM_13,
96 SSD1309_LOW_COL_START_ADDR_PAM_14,
97 SSD1309_LOW_COL_START_ADDR_PAM_15
98}SSD1309_LOW_COL_START_ADDR_PAM_te;
99
105 typedef enum {
106 SSD1309_HIGH_COL_START_ADDR_PAM_0,
107 SSD1309_HIGH_COL_START_ADDR_PAM_1,
108 SSD1309_HIGH_COL_START_ADDR_PAM_2,
109 SSD1309_HIGH_COL_START_ADDR_PAM_3,
110 SSD1309_HIGH_COL_START_ADDR_PAM_4,
111 SSD1309_HIGH_COL_START_ADDR_PAM_5,
112 SSD1309_HIGH_COL_START_ADDR_PAM_6,
113 SSD1309_HIGH_COL_START_ADDR_PAM_7,
114}SSD1309_HIGH_COL_START_ADDR_PAM_te;
115
122typedef enum {
123 SSD1309_MEM_ADDR_MODE_HAM,
124 SSD1309_MEM_ADDR_MODE_VAM,
125 SSD1309_MEM_ADDR_MODE_PAM
126}SSD1309_MEM_ADDR_MODE_te;
127
132typedef enum {
133 SSD1309_COL_ADDR_START_HAM_VAM_0,
134 SSD1309_COL_ADDR_START_HAM_VAM_1,
135 SSD1309_COL_ADDR_START_HAM_VAM_2,
136 SSD1309_COL_ADDR_START_HAM_VAM_3,
137 SSD1309_COL_ADDR_START_HAM_VAM_4,
138 SSD1309_COL_ADDR_START_HAM_VAM_5,
139 SSD1309_COL_ADDR_START_HAM_VAM_6,
140 SSD1309_COL_ADDR_START_HAM_VAM_7,
141 SSD1309_COL_ADDR_START_HAM_VAM_8,
142 SSD1309_COL_ADDR_START_HAM_VAM_9,
143 SSD1309_COL_ADDR_START_HAM_VAM_10,
144 SSD1309_COL_ADDR_START_HAM_VAM_11,
145 SSD1309_COL_ADDR_START_HAM_VAM_12,
146 SSD1309_COL_ADDR_START_HAM_VAM_13,
147 SSD1309_COL_ADDR_START_HAM_VAM_14,
148 SSD1309_COL_ADDR_START_HAM_VAM_15,
149 SSD1309_COL_ADDR_START_HAM_VAM_16,
150 SSD1309_COL_ADDR_START_HAM_VAM_17,
151 SSD1309_COL_ADDR_START_HAM_VAM_18,
152 SSD1309_COL_ADDR_START_HAM_VAM_19,
153 SSD1309_COL_ADDR_START_HAM_VAM_20,
154 SSD1309_COL_ADDR_START_HAM_VAM_21,
155 SSD1309_COL_ADDR_START_HAM_VAM_22,
156 SSD1309_COL_ADDR_START_HAM_VAM_23,
157 SSD1309_COL_ADDR_START_HAM_VAM_24,
158 SSD1309_COL_ADDR_START_HAM_VAM_25,
159 SSD1309_COL_ADDR_START_HAM_VAM_26,
160 SSD1309_COL_ADDR_START_HAM_VAM_27,
161 SSD1309_COL_ADDR_START_HAM_VAM_28,
162 SSD1309_COL_ADDR_START_HAM_VAM_29,
163 SSD1309_COL_ADDR_START_HAM_VAM_30,
164 SSD1309_COL_ADDR_START_HAM_VAM_31,
165 SSD1309_COL_ADDR_START_HAM_VAM_32,
166 SSD1309_COL_ADDR_START_HAM_VAM_33,
167 SSD1309_COL_ADDR_START_HAM_VAM_34,
168 SSD1309_COL_ADDR_START_HAM_VAM_35,
169 SSD1309_COL_ADDR_START_HAM_VAM_36,
170 SSD1309_COL_ADDR_START_HAM_VAM_37,
171 SSD1309_COL_ADDR_START_HAM_VAM_38,
172 SSD1309_COL_ADDR_START_HAM_VAM_39,
173 SSD1309_COL_ADDR_START_HAM_VAM_40,
174 SSD1309_COL_ADDR_START_HAM_VAM_41,
175 SSD1309_COL_ADDR_START_HAM_VAM_42,
176 SSD1309_COL_ADDR_START_HAM_VAM_43,
177 SSD1309_COL_ADDR_START_HAM_VAM_44,
178 SSD1309_COL_ADDR_START_HAM_VAM_45,
179 SSD1309_COL_ADDR_START_HAM_VAM_46,
180 SSD1309_COL_ADDR_START_HAM_VAM_47,
181 SSD1309_COL_ADDR_START_HAM_VAM_48,
182 SSD1309_COL_ADDR_START_HAM_VAM_49,
183 SSD1309_COL_ADDR_START_HAM_VAM_50,
184 SSD1309_COL_ADDR_START_HAM_VAM_51,
185 SSD1309_COL_ADDR_START_HAM_VAM_52,
186 SSD1309_COL_ADDR_START_HAM_VAM_53,
187 SSD1309_COL_ADDR_START_HAM_VAM_54,
188 SSD1309_COL_ADDR_START_HAM_VAM_55,
189 SSD1309_COL_ADDR_START_HAM_VAM_56,
190 SSD1309_COL_ADDR_START_HAM_VAM_57,
191 SSD1309_COL_ADDR_START_HAM_VAM_58,
192 SSD1309_COL_ADDR_START_HAM_VAM_59,
193 SSD1309_COL_ADDR_START_HAM_VAM_60,
194 SSD1309_COL_ADDR_START_HAM_VAM_61,
195 SSD1309_COL_ADDR_START_HAM_VAM_62,
196 SSD1309_COL_ADDR_START_HAM_VAM_63,
197 SSD1309_COL_ADDR_START_HAM_VAM_64,
198 SSD1309_COL_ADDR_START_HAM_VAM_65,
199 SSD1309_COL_ADDR_START_HAM_VAM_66,
200 SSD1309_COL_ADDR_START_HAM_VAM_67,
201 SSD1309_COL_ADDR_START_HAM_VAM_68,
202 SSD1309_COL_ADDR_START_HAM_VAM_69,
203 SSD1309_COL_ADDR_START_HAM_VAM_70,
204 SSD1309_COL_ADDR_START_HAM_VAM_71,
205 SSD1309_COL_ADDR_START_HAM_VAM_72,
206 SSD1309_COL_ADDR_START_HAM_VAM_73,
207 SSD1309_COL_ADDR_START_HAM_VAM_74,
208 SSD1309_COL_ADDR_START_HAM_VAM_75,
209 SSD1309_COL_ADDR_START_HAM_VAM_76,
210 SSD1309_COL_ADDR_START_HAM_VAM_77,
211 SSD1309_COL_ADDR_START_HAM_VAM_78,
212 SSD1309_COL_ADDR_START_HAM_VAM_79,
213 SSD1309_COL_ADDR_START_HAM_VAM_80,
214 SSD1309_COL_ADDR_START_HAM_VAM_81,
215 SSD1309_COL_ADDR_START_HAM_VAM_82,
216 SSD1309_COL_ADDR_START_HAM_VAM_83,
217 SSD1309_COL_ADDR_START_HAM_VAM_84,
218 SSD1309_COL_ADDR_START_HAM_VAM_85,
219 SSD1309_COL_ADDR_START_HAM_VAM_86,
220 SSD1309_COL_ADDR_START_HAM_VAM_87,
221 SSD1309_COL_ADDR_START_HAM_VAM_88,
222 SSD1309_COL_ADDR_START_HAM_VAM_89,
223 SSD1309_COL_ADDR_START_HAM_VAM_90,
224 SSD1309_COL_ADDR_START_HAM_VAM_91,
225 SSD1309_COL_ADDR_START_HAM_VAM_92,
226 SSD1309_COL_ADDR_START_HAM_VAM_93,
227 SSD1309_COL_ADDR_START_HAM_VAM_94,
228 SSD1309_COL_ADDR_START_HAM_VAM_95,
229 SSD1309_COL_ADDR_START_HAM_VAM_96,
230 SSD1309_COL_ADDR_START_HAM_VAM_97,
231 SSD1309_COL_ADDR_START_HAM_VAM_98,
232 SSD1309_COL_ADDR_START_HAM_VAM_99,
233 SSD1309_COL_ADDR_START_HAM_VAM_100,
234 SSD1309_COL_ADDR_START_HAM_VAM_101,
235 SSD1309_COL_ADDR_START_HAM_VAM_102,
236 SSD1309_COL_ADDR_START_HAM_VAM_103,
237 SSD1309_COL_ADDR_START_HAM_VAM_104,
238 SSD1309_COL_ADDR_START_HAM_VAM_105,
239 SSD1309_COL_ADDR_START_HAM_VAM_106,
240 SSD1309_COL_ADDR_START_HAM_VAM_107,
241 SSD1309_COL_ADDR_START_HAM_VAM_108,
242 SSD1309_COL_ADDR_START_HAM_VAM_109,
243 SSD1309_COL_ADDR_START_HAM_VAM_110,
244 SSD1309_COL_ADDR_START_HAM_VAM_111,
245 SSD1309_COL_ADDR_START_HAM_VAM_112,
246 SSD1309_COL_ADDR_START_HAM_VAM_113,
247 SSD1309_COL_ADDR_START_HAM_VAM_114,
248 SSD1309_COL_ADDR_START_HAM_VAM_115,
249 SSD1309_COL_ADDR_START_HAM_VAM_116,
250 SSD1309_COL_ADDR_START_HAM_VAM_117,
251 SSD1309_COL_ADDR_START_HAM_VAM_118,
252 SSD1309_COL_ADDR_START_HAM_VAM_119,
253 SSD1309_COL_ADDR_START_HAM_VAM_120,
254 SSD1309_COL_ADDR_START_HAM_VAM_121,
255 SSD1309_COL_ADDR_START_HAM_VAM_122,
256 SSD1309_COL_ADDR_START_HAM_VAM_123,
257 SSD1309_COL_ADDR_START_HAM_VAM_124,
258 SSD1309_COL_ADDR_START_HAM_VAM_125,
259 SSD1309_COL_ADDR_START_HAM_VAM_126,
260 SSD1309_COL_ADDR_START_HAM_VAM_127
261}SSD1309_COL_ADDR_START_HAM_VAM_te;
262
267typedef enum {
268 SSD1309_COL_ADDR_END_HAM_VAM_0,
269 SSD1309_COL_ADDR_END_HAM_VAM_1,
270 SSD1309_COL_ADDR_END_HAM_VAM_2,
271 SSD1309_COL_ADDR_END_HAM_VAM_3,
272 SSD1309_COL_ADDR_END_HAM_VAM_4,
273 SSD1309_COL_ADDR_END_HAM_VAM_5,
274 SSD1309_COL_ADDR_END_HAM_VAM_6,
275 SSD1309_COL_ADDR_END_HAM_VAM_7,
276 SSD1309_COL_ADDR_END_HAM_VAM_8,
277 SSD1309_COL_ADDR_END_HAM_VAM_9,
278 SSD1309_COL_ADDR_END_HAM_VAM_10,
279 SSD1309_COL_ADDR_END_HAM_VAM_11,
280 SSD1309_COL_ADDR_END_HAM_VAM_12,
281 SSD1309_COL_ADDR_END_HAM_VAM_13,
282 SSD1309_COL_ADDR_END_HAM_VAM_14,
283 SSD1309_COL_ADDR_END_HAM_VAM_15,
284 SSD1309_COL_ADDR_END_HAM_VAM_16,
285 SSD1309_COL_ADDR_END_HAM_VAM_17,
286 SSD1309_COL_ADDR_END_HAM_VAM_18,
287 SSD1309_COL_ADDR_END_HAM_VAM_19,
288 SSD1309_COL_ADDR_END_HAM_VAM_20,
289 SSD1309_COL_ADDR_END_HAM_VAM_21,
290 SSD1309_COL_ADDR_END_HAM_VAM_22,
291 SSD1309_COL_ADDR_END_HAM_VAM_23,
292 SSD1309_COL_ADDR_END_HAM_VAM_24,
293 SSD1309_COL_ADDR_END_HAM_VAM_25,
294 SSD1309_COL_ADDR_END_HAM_VAM_26,
295 SSD1309_COL_ADDR_END_HAM_VAM_27,
296 SSD1309_COL_ADDR_END_HAM_VAM_28,
297 SSD1309_COL_ADDR_END_HAM_VAM_29,
298 SSD1309_COL_ADDR_END_HAM_VAM_30,
299 SSD1309_COL_ADDR_END_HAM_VAM_31,
300 SSD1309_COL_ADDR_END_HAM_VAM_32,
301 SSD1309_COL_ADDR_END_HAM_VAM_33,
302 SSD1309_COL_ADDR_END_HAM_VAM_34,
303 SSD1309_COL_ADDR_END_HAM_VAM_35,
304 SSD1309_COL_ADDR_END_HAM_VAM_36,
305 SSD1309_COL_ADDR_END_HAM_VAM_37,
306 SSD1309_COL_ADDR_END_HAM_VAM_38,
307 SSD1309_COL_ADDR_END_HAM_VAM_39,
308 SSD1309_COL_ADDR_END_HAM_VAM_40,
309 SSD1309_COL_ADDR_END_HAM_VAM_41,
310 SSD1309_COL_ADDR_END_HAM_VAM_42,
311 SSD1309_COL_ADDR_END_HAM_VAM_43,
312 SSD1309_COL_ADDR_END_HAM_VAM_44,
313 SSD1309_COL_ADDR_END_HAM_VAM_45,
314 SSD1309_COL_ADDR_END_HAM_VAM_46,
315 SSD1309_COL_ADDR_END_HAM_VAM_47,
316 SSD1309_COL_ADDR_END_HAM_VAM_48,
317 SSD1309_COL_ADDR_END_HAM_VAM_49,
318 SSD1309_COL_ADDR_END_HAM_VAM_50,
319 SSD1309_COL_ADDR_END_HAM_VAM_51,
320 SSD1309_COL_ADDR_END_HAM_VAM_52,
321 SSD1309_COL_ADDR_END_HAM_VAM_53,
322 SSD1309_COL_ADDR_END_HAM_VAM_54,
323 SSD1309_COL_ADDR_END_HAM_VAM_55,
324 SSD1309_COL_ADDR_END_HAM_VAM_56,
325 SSD1309_COL_ADDR_END_HAM_VAM_57,
326 SSD1309_COL_ADDR_END_HAM_VAM_58,
327 SSD1309_COL_ADDR_END_HAM_VAM_59,
328 SSD1309_COL_ADDR_END_HAM_VAM_60,
329 SSD1309_COL_ADDR_END_HAM_VAM_61,
330 SSD1309_COL_ADDR_END_HAM_VAM_62,
331 SSD1309_COL_ADDR_END_HAM_VAM_63,
332 SSD1309_COL_ADDR_END_HAM_VAM_64,
333 SSD1309_COL_ADDR_END_HAM_VAM_65,
334 SSD1309_COL_ADDR_END_HAM_VAM_66,
335 SSD1309_COL_ADDR_END_HAM_VAM_67,
336 SSD1309_COL_ADDR_END_HAM_VAM_68,
337 SSD1309_COL_ADDR_END_HAM_VAM_69,
338 SSD1309_COL_ADDR_END_HAM_VAM_70,
339 SSD1309_COL_ADDR_END_HAM_VAM_71,
340 SSD1309_COL_ADDR_END_HAM_VAM_72,
341 SSD1309_COL_ADDR_END_HAM_VAM_73,
342 SSD1309_COL_ADDR_END_HAM_VAM_74,
343 SSD1309_COL_ADDR_END_HAM_VAM_75,
344 SSD1309_COL_ADDR_END_HAM_VAM_76,
345 SSD1309_COL_ADDR_END_HAM_VAM_77,
346 SSD1309_COL_ADDR_END_HAM_VAM_78,
347 SSD1309_COL_ADDR_END_HAM_VAM_79,
348 SSD1309_COL_ADDR_END_HAM_VAM_80,
349 SSD1309_COL_ADDR_END_HAM_VAM_81,
350 SSD1309_COL_ADDR_END_HAM_VAM_82,
351 SSD1309_COL_ADDR_END_HAM_VAM_83,
352 SSD1309_COL_ADDR_END_HAM_VAM_84,
353 SSD1309_COL_ADDR_END_HAM_VAM_85,
354 SSD1309_COL_ADDR_END_HAM_VAM_86,
355 SSD1309_COL_ADDR_END_HAM_VAM_87,
356 SSD1309_COL_ADDR_END_HAM_VAM_88,
357 SSD1309_COL_ADDR_END_HAM_VAM_89,
358 SSD1309_COL_ADDR_END_HAM_VAM_90,
359 SSD1309_COL_ADDR_END_HAM_VAM_91,
360 SSD1309_COL_ADDR_END_HAM_VAM_92,
361 SSD1309_COL_ADDR_END_HAM_VAM_93,
362 SSD1309_COL_ADDR_END_HAM_VAM_94,
363 SSD1309_COL_ADDR_END_HAM_VAM_95,
364 SSD1309_COL_ADDR_END_HAM_VAM_96,
365 SSD1309_COL_ADDR_END_HAM_VAM_97,
366 SSD1309_COL_ADDR_END_HAM_VAM_98,
367 SSD1309_COL_ADDR_END_HAM_VAM_99,
368 SSD1309_COL_ADDR_END_HAM_VAM_100,
369 SSD1309_COL_ADDR_END_HAM_VAM_101,
370 SSD1309_COL_ADDR_END_HAM_VAM_102,
371 SSD1309_COL_ADDR_END_HAM_VAM_103,
372 SSD1309_COL_ADDR_END_HAM_VAM_104,
373 SSD1309_COL_ADDR_END_HAM_VAM_105,
374 SSD1309_COL_ADDR_END_HAM_VAM_106,
375 SSD1309_COL_ADDR_END_HAM_VAM_107,
376 SSD1309_COL_ADDR_END_HAM_VAM_108,
377 SSD1309_COL_ADDR_END_HAM_VAM_109,
378 SSD1309_COL_ADDR_END_HAM_VAM_110,
379 SSD1309_COL_ADDR_END_HAM_VAM_111,
380 SSD1309_COL_ADDR_END_HAM_VAM_112,
381 SSD1309_COL_ADDR_END_HAM_VAM_113,
382 SSD1309_COL_ADDR_END_HAM_VAM_114,
383 SSD1309_COL_ADDR_END_HAM_VAM_115,
384 SSD1309_COL_ADDR_END_HAM_VAM_116,
385 SSD1309_COL_ADDR_END_HAM_VAM_117,
386 SSD1309_COL_ADDR_END_HAM_VAM_118,
387 SSD1309_COL_ADDR_END_HAM_VAM_119,
388 SSD1309_COL_ADDR_END_HAM_VAM_120,
389 SSD1309_COL_ADDR_END_HAM_VAM_121,
390 SSD1309_COL_ADDR_END_HAM_VAM_122,
391 SSD1309_COL_ADDR_END_HAM_VAM_123,
392 SSD1309_COL_ADDR_END_HAM_VAM_124,
393 SSD1309_COL_ADDR_END_HAM_VAM_125,
394 SSD1309_COL_ADDR_END_HAM_VAM_126,
395 SSD1309_COL_ADDR_END_HAM_VAM_127
396}SSD1309_COL_ADDR_END_HAM_VAM_te;
397
402typedef enum {
403 SSD1309_PAGE_ADDR_START_HAM_VAM_0,
404 SSD1309_PAGE_ADDR_START_HAM_VAM_1,
405 SSD1309_PAGE_ADDR_START_HAM_VAM_2,
406 SSD1309_PAGE_ADDR_START_HAM_VAM_3,
407 SSD1309_PAGE_ADDR_START_HAM_VAM_4,
408 SSD1309_PAGE_ADDR_START_HAM_VAM_5,
409 SSD1309_PAGE_ADDR_START_HAM_VAM_6,
410 SSD1309_PAGE_ADDR_START_HAM_VAM_7
411}SSD1309_PAGE_ADDR_START_HAM_VAM_te;
412
417 typedef enum {
418 SSD1309_PAGE_ADDR_END_HAM_VAM_0,
419 SSD1309_PAGE_ADDR_END_HAM_VAM_1,
420 SSD1309_PAGE_ADDR_END_HAM_VAM_2,
421 SSD1309_PAGE_ADDR_END_HAM_VAM_3,
422 SSD1309_PAGE_ADDR_END_HAM_VAM_4,
423 SSD1309_PAGE_ADDR_END_HAM_VAM_5,
424 SSD1309_PAGE_ADDR_END_HAM_VAM_6,
425 SSD1309_PAGE_ADDR_END_HAM_VAM_7
426}SSD1309_PAGE_ADDR_END_HAM_VAM_te;
427
432typedef enum {
433 SSD1309_START_LINE_0,
434 SSD1309_START_LINE_1,
435 SSD1309_START_LINE_2,
436 SSD1309_START_LINE_3,
437 SSD1309_START_LINE_4,
438 SSD1309_START_LINE_5,
439 SSD1309_START_LINE_6,
440 SSD1309_START_LINE_7,
441 SSD1309_START_LINE_8,
442 SSD1309_START_LINE_9,
443 SSD1309_START_LINE_10,
444 SSD1309_START_LINE_11,
445 SSD1309_START_LINE_12,
446 SSD1309_START_LINE_13,
447 SSD1309_START_LINE_14,
448 SSD1309_START_LINE_15,
449 SSD1309_START_LINE_16,
450 SSD1309_START_LINE_17,
451 SSD1309_START_LINE_18,
452 SSD1309_START_LINE_19,
453 SSD1309_START_LINE_20,
454 SSD1309_START_LINE_21,
455 SSD1309_START_LINE_22,
456 SSD1309_START_LINE_23,
457 SSD1309_START_LINE_24,
458 SSD1309_START_LINE_25,
459 SSD1309_START_LINE_26,
460 SSD1309_START_LINE_27,
461 SSD1309_START_LINE_28,
462 SSD1309_START_LINE_29,
463 SSD1309_START_LINE_30,
464 SSD1309_START_LINE_31,
465 SSD1309_START_LINE_32,
466 SSD1309_START_LINE_33,
467 SSD1309_START_LINE_34,
468 SSD1309_START_LINE_35,
469 SSD1309_START_LINE_36,
470 SSD1309_START_LINE_37,
471 SSD1309_START_LINE_38,
472 SSD1309_START_LINE_39,
473 SSD1309_START_LINE_40,
474 SSD1309_START_LINE_41,
475 SSD1309_START_LINE_42,
476 SSD1309_START_LINE_43,
477 SSD1309_START_LINE_44,
478 SSD1309_START_LINE_45,
479 SSD1309_START_LINE_46,
480 SSD1309_START_LINE_47,
481 SSD1309_START_LINE_48,
482 SSD1309_START_LINE_49,
483 SSD1309_START_LINE_50,
484 SSD1309_START_LINE_51,
485 SSD1309_START_LINE_52,
486 SSD1309_START_LINE_53,
487 SSD1309_START_LINE_54,
488 SSD1309_START_LINE_55,
489 SSD1309_START_LINE_56,
490 SSD1309_START_LINE_57,
491 SSD1309_START_LINE_58,
492 SSD1309_START_LINE_59,
493 SSD1309_START_LINE_60,
494 SSD1309_START_LINE_61,
495 SSD1309_START_LINE_62,
496 SSD1309_START_LINE_63
497}SSD1309_START_LINE_te;
498
503typedef enum {
504 SSD1309_CONTRAST_0,
505 SSD1309_CONTRAST_1,
506 SSD1309_CONTRAST_2,
507 SSD1309_CONTRAST_3,
508 SSD1309_CONTRAST_4,
509 SSD1309_CONTRAST_5,
510 SSD1309_CONTRAST_6,
511 SSD1309_CONTRAST_7,
512 SSD1309_CONTRAST_8,
513 SSD1309_CONTRAST_9,
514 SSD1309_CONTRAST_10,
515 SSD1309_CONTRAST_11,
516 SSD1309_CONTRAST_12,
517 SSD1309_CONTRAST_13,
518 SSD1309_CONTRAST_14,
519 SSD1309_CONTRAST_15,
520 SSD1309_CONTRAST_16,
521 SSD1309_CONTRAST_17,
522 SSD1309_CONTRAST_18,
523 SSD1309_CONTRAST_19,
524 SSD1309_CONTRAST_20,
525 SSD1309_CONTRAST_21,
526 SSD1309_CONTRAST_22,
527 SSD1309_CONTRAST_23,
528 SSD1309_CONTRAST_24,
529 SSD1309_CONTRAST_25,
530 SSD1309_CONTRAST_26,
531 SSD1309_CONTRAST_27,
532 SSD1309_CONTRAST_28,
533 SSD1309_CONTRAST_29,
534 SSD1309_CONTRAST_30,
535 SSD1309_CONTRAST_31,
536 SSD1309_CONTRAST_32,
537 SSD1309_CONTRAST_33,
538 SSD1309_CONTRAST_34,
539 SSD1309_CONTRAST_35,
540 SSD1309_CONTRAST_36,
541 SSD1309_CONTRAST_37,
542 SSD1309_CONTRAST_38,
543 SSD1309_CONTRAST_39,
544 SSD1309_CONTRAST_40,
545 SSD1309_CONTRAST_41,
546 SSD1309_CONTRAST_42,
547 SSD1309_CONTRAST_43,
548 SSD1309_CONTRAST_44,
549 SSD1309_CONTRAST_45,
550 SSD1309_CONTRAST_46,
551 SSD1309_CONTRAST_47,
552 SSD1309_CONTRAST_48,
553 SSD1309_CONTRAST_49,
554 SSD1309_CONTRAST_50,
555 SSD1309_CONTRAST_51,
556 SSD1309_CONTRAST_52,
557 SSD1309_CONTRAST_53,
558 SSD1309_CONTRAST_54,
559 SSD1309_CONTRAST_55,
560 SSD1309_CONTRAST_56,
561 SSD1309_CONTRAST_57,
562 SSD1309_CONTRAST_58,
563 SSD1309_CONTRAST_59,
564 SSD1309_CONTRAST_60,
565 SSD1309_CONTRAST_61,
566 SSD1309_CONTRAST_62,
567 SSD1309_CONTRAST_63,
568 SSD1309_CONTRAST_64,
569 SSD1309_CONTRAST_65,
570 SSD1309_CONTRAST_66,
571 SSD1309_CONTRAST_67,
572 SSD1309_CONTRAST_68,
573 SSD1309_CONTRAST_69,
574 SSD1309_CONTRAST_70,
575 SSD1309_CONTRAST_71,
576 SSD1309_CONTRAST_72,
577 SSD1309_CONTRAST_73,
578 SSD1309_CONTRAST_74,
579 SSD1309_CONTRAST_75,
580 SSD1309_CONTRAST_76,
581 SSD1309_CONTRAST_77,
582 SSD1309_CONTRAST_78,
583 SSD1309_CONTRAST_79,
584 SSD1309_CONTRAST_80,
585 SSD1309_CONTRAST_81,
586 SSD1309_CONTRAST_82,
587 SSD1309_CONTRAST_83,
588 SSD1309_CONTRAST_84,
589 SSD1309_CONTRAST_85,
590 SSD1309_CONTRAST_86,
591 SSD1309_CONTRAST_87,
592 SSD1309_CONTRAST_88,
593 SSD1309_CONTRAST_89,
594 SSD1309_CONTRAST_90,
595 SSD1309_CONTRAST_91,
596 SSD1309_CONTRAST_92,
597 SSD1309_CONTRAST_93,
598 SSD1309_CONTRAST_94,
599 SSD1309_CONTRAST_95,
600 SSD1309_CONTRAST_96,
601 SSD1309_CONTRAST_97,
602 SSD1309_CONTRAST_98,
603 SSD1309_CONTRAST_99,
604 SSD1309_CONTRAST_100,
605 SSD1309_CONTRAST_101,
606 SSD1309_CONTRAST_102,
607 SSD1309_CONTRAST_103,
608 SSD1309_CONTRAST_104,
609 SSD1309_CONTRAST_105,
610 SSD1309_CONTRAST_106,
611 SSD1309_CONTRAST_107,
612 SSD1309_CONTRAST_108,
613 SSD1309_CONTRAST_109,
614 SSD1309_CONTRAST_110,
615 SSD1309_CONTRAST_111,
616 SSD1309_CONTRAST_112,
617 SSD1309_CONTRAST_113,
618 SSD1309_CONTRAST_114,
619 SSD1309_CONTRAST_115,
620 SSD1309_CONTRAST_116,
621 SSD1309_CONTRAST_117,
622 SSD1309_CONTRAST_118,
623 SSD1309_CONTRAST_119,
624 SSD1309_CONTRAST_120,
625 SSD1309_CONTRAST_121,
626 SSD1309_CONTRAST_122,
627 SSD1309_CONTRAST_123,
628 SSD1309_CONTRAST_124,
629 SSD1309_CONTRAST_125,
630 SSD1309_CONTRAST_126,
631 SSD1309_CONTRAST_127,
632 SSD1309_CONTRAST_128,
633 SSD1309_CONTRAST_129,
634 SSD1309_CONTRAST_130,
635 SSD1309_CONTRAST_131,
636 SSD1309_CONTRAST_132,
637 SSD1309_CONTRAST_133,
638 SSD1309_CONTRAST_134,
639 SSD1309_CONTRAST_135,
640 SSD1309_CONTRAST_136,
641 SSD1309_CONTRAST_137,
642 SSD1309_CONTRAST_138,
643 SSD1309_CONTRAST_139,
644 SSD1309_CONTRAST_140,
645 SSD1309_CONTRAST_141,
646 SSD1309_CONTRAST_142,
647 SSD1309_CONTRAST_143,
648 SSD1309_CONTRAST_144,
649 SSD1309_CONTRAST_145,
650 SSD1309_CONTRAST_146,
651 SSD1309_CONTRAST_147,
652 SSD1309_CONTRAST_148,
653 SSD1309_CONTRAST_149,
654 SSD1309_CONTRAST_150,
655 SSD1309_CONTRAST_151,
656 SSD1309_CONTRAST_152,
657 SSD1309_CONTRAST_153,
658 SSD1309_CONTRAST_154,
659 SSD1309_CONTRAST_155,
660 SSD1309_CONTRAST_156,
661 SSD1309_CONTRAST_157,
662 SSD1309_CONTRAST_158,
663 SSD1309_CONTRAST_159,
664 SSD1309_CONTRAST_160,
665 SSD1309_CONTRAST_161,
666 SSD1309_CONTRAST_162,
667 SSD1309_CONTRAST_163,
668 SSD1309_CONTRAST_164,
669 SSD1309_CONTRAST_165,
670 SSD1309_CONTRAST_166,
671 SSD1309_CONTRAST_167,
672 SSD1309_CONTRAST_168,
673 SSD1309_CONTRAST_169,
674 SSD1309_CONTRAST_170,
675 SSD1309_CONTRAST_171,
676 SSD1309_CONTRAST_172,
677 SSD1309_CONTRAST_173,
678 SSD1309_CONTRAST_174,
679 SSD1309_CONTRAST_175,
680 SSD1309_CONTRAST_176,
681 SSD1309_CONTRAST_177,
682 SSD1309_CONTRAST_178,
683 SSD1309_CONTRAST_179,
684 SSD1309_CONTRAST_180,
685 SSD1309_CONTRAST_181,
686 SSD1309_CONTRAST_182,
687 SSD1309_CONTRAST_183,
688 SSD1309_CONTRAST_184,
689 SSD1309_CONTRAST_185,
690 SSD1309_CONTRAST_186,
691 SSD1309_CONTRAST_187,
692 SSD1309_CONTRAST_188,
693 SSD1309_CONTRAST_189,
694 SSD1309_CONTRAST_190,
695 SSD1309_CONTRAST_191,
696 SSD1309_CONTRAST_192,
697 SSD1309_CONTRAST_193,
698 SSD1309_CONTRAST_194,
699 SSD1309_CONTRAST_195,
700 SSD1309_CONTRAST_196,
701 SSD1309_CONTRAST_197,
702 SSD1309_CONTRAST_198,
703 SSD1309_CONTRAST_199,
704 SSD1309_CONTRAST_200,
705 SSD1309_CONTRAST_201,
706 SSD1309_CONTRAST_202,
707 SSD1309_CONTRAST_203,
708 SSD1309_CONTRAST_204,
709 SSD1309_CONTRAST_205,
710 SSD1309_CONTRAST_206,
711 SSD1309_CONTRAST_207,
712 SSD1309_CONTRAST_208,
713 SSD1309_CONTRAST_209,
714 SSD1309_CONTRAST_210,
715 SSD1309_CONTRAST_211,
716 SSD1309_CONTRAST_212,
717 SSD1309_CONTRAST_213,
718 SSD1309_CONTRAST_214,
719 SSD1309_CONTRAST_215,
720 SSD1309_CONTRAST_216,
721 SSD1309_CONTRAST_217,
722 SSD1309_CONTRAST_218,
723 SSD1309_CONTRAST_219,
724 SSD1309_CONTRAST_220,
725 SSD1309_CONTRAST_221,
726 SSD1309_CONTRAST_222,
727 SSD1309_CONTRAST_223,
728 SSD1309_CONTRAST_224,
729 SSD1309_CONTRAST_225,
730 SSD1309_CONTRAST_226,
731 SSD1309_CONTRAST_227,
732 SSD1309_CONTRAST_228,
733 SSD1309_CONTRAST_229,
734 SSD1309_CONTRAST_230,
735 SSD1309_CONTRAST_231,
736 SSD1309_CONTRAST_232,
737 SSD1309_CONTRAST_233,
738 SSD1309_CONTRAST_234,
739 SSD1309_CONTRAST_235,
740 SSD1309_CONTRAST_236,
741 SSD1309_CONTRAST_237,
742 SSD1309_CONTRAST_238,
743 SSD1309_CONTRAST_239,
744 SSD1309_CONTRAST_240,
745 SSD1309_CONTRAST_241,
746 SSD1309_CONTRAST_242,
747 SSD1309_CONTRAST_243,
748 SSD1309_CONTRAST_244,
749 SSD1309_CONTRAST_245,
750 SSD1309_CONTRAST_246,
751 SSD1309_CONTRAST_247,
752 SSD1309_CONTRAST_248,
753 SSD1309_CONTRAST_249,
754 SSD1309_CONTRAST_250,
755 SSD1309_CONTRAST_251,
756 SSD1309_CONTRAST_252,
757 SSD1309_CONTRAST_253,
758 SSD1309_CONTRAST_254,
759 SSD1309_CONTRAST_255
760}SSD1309_CONTRAST_te;
761
766typedef enum {
767 SSD1309_HORIZONTAL_FLIP_FALSE,
768 SSD1309_HORIZONTAL_FLIP_TRUE
769}SSD1309_HORIZONTAL_FLIP_te;
770
775typedef enum {
776 SSD1309_INVERSE_MODE_FALSE,
777 SSD1309_INVERSE_MODE_TRUE
778}SSD1309_INVERSE_MODE_te;
779
784typedef enum {
785 SSD1309_MULTIPLEX_RATIO_16 = 15,
786 SSD1309_MULTIPLEX_RATIO_17,
787 SSD1309_MULTIPLEX_RATIO_18,
788 SSD1309_MULTIPLEX_RATIO_19,
789 SSD1309_MULTIPLEX_RATIO_20,
790 SSD1309_MULTIPLEX_RATIO_21,
791 SSD1309_MULTIPLEX_RATIO_22,
792 SSD1309_MULTIPLEX_RATIO_23,
793 SSD1309_MULTIPLEX_RATIO_24,
794 SSD1309_MULTIPLEX_RATIO_25,
795 SSD1309_MULTIPLEX_RATIO_26,
796 SSD1309_MULTIPLEX_RATIO_27,
797 SSD1309_MULTIPLEX_RATIO_28,
798 SSD1309_MULTIPLEX_RATIO_29,
799 SSD1309_MULTIPLEX_RATIO_30,
800 SSD1309_MULTIPLEX_RATIO_31,
801 SSD1309_MULTIPLEX_RATIO_32,
802 SSD1309_MULTIPLEX_RATIO_33,
803 SSD1309_MULTIPLEX_RATIO_34,
804 SSD1309_MULTIPLEX_RATIO_35,
805 SSD1309_MULTIPLEX_RATIO_36,
806 SSD1309_MULTIPLEX_RATIO_37,
807 SSD1309_MULTIPLEX_RATIO_38,
808 SSD1309_MULTIPLEX_RATIO_39,
809 SSD1309_MULTIPLEX_RATIO_40,
810 SSD1309_MULTIPLEX_RATIO_41,
811 SSD1309_MULTIPLEX_RATIO_42,
812 SSD1309_MULTIPLEX_RATIO_43,
813 SSD1309_MULTIPLEX_RATIO_44,
814 SSD1309_MULTIPLEX_RATIO_45,
815 SSD1309_MULTIPLEX_RATIO_46,
816 SSD1309_MULTIPLEX_RATIO_47,
817 SSD1309_MULTIPLEX_RATIO_48,
818 SSD1309_MULTIPLEX_RATIO_49,
819 SSD1309_MULTIPLEX_RATIO_50,
820 SSD1309_MULTIPLEX_RATIO_51,
821 SSD1309_MULTIPLEX_RATIO_52,
822 SSD1309_MULTIPLEX_RATIO_53,
823 SSD1309_MULTIPLEX_RATIO_54,
824 SSD1309_MULTIPLEX_RATIO_55,
825 SSD1309_MULTIPLEX_RATIO_56,
826 SSD1309_MULTIPLEX_RATIO_57,
827 SSD1309_MULTIPLEX_RATIO_58,
828 SSD1309_MULTIPLEX_RATIO_59,
829 SSD1309_MULTIPLEX_RATIO_60,
830 SSD1309_MULTIPLEX_RATIO_61,
831 SSD1309_MULTIPLEX_RATIO_62,
832 SSD1309_MULTIPLEX_RATIO_63,
833 SSD1309_MULTIPLEX_RATIO_64
834}SSD1309_MULTIPLEX_RATIO_te;
835
840typedef enum {
841 SSD1309_PAGE_START_ADDR_PAM_0,
842 SSD1309_PAGE_START_ADDR_PAM_1,
843 SSD1309_PAGE_START_ADDR_PAM_2,
844 SSD1309_PAGE_START_ADDR_PAM_3,
845 SSD1309_PAGE_START_ADDR_PAM_4,
846 SSD1309_PAGE_START_ADDR_PAM_5,
847 SSD1309_PAGE_START_ADDR_PAM_6,
848 SSD1309_PAGE_START_ADDR_PAM_7,
849}SSD1309_PAGE_START_ADDR_PAM_te;
850
855typedef enum {
856 SSD1309_VERTICAL_FLIP_FALSE,
857 SSD1309_VERTICAL_FLIP_TRUE = 8
858}SSD1309_VERTICAL_FLIP_te;
859
864typedef enum {
865 SSD1309_OFFSET_0 = 0,
866 SSD1309_OFFSET_1,
867 SSD1309_OFFSET_2,
868 SSD1309_OFFSET_3,
869 SSD1309_OFFSET_4,
870 SSD1309_OFFSET_5,
871 SSD1309_OFFSET_6,
872 SSD1309_OFFSET_7,
873 SSD1309_OFFSET_8,
874 SSD1309_OFFSET_9,
875 SSD1309_OFFSET_10,
876 SSD1309_OFFSET_11,
877 SSD1309_OFFSET_12,
878 SSD1309_OFFSET_13,
879 SSD1309_OFFSET_14,
880 SSD1309_OFFSET_15,
881 SSD1309_OFFSET_16,
882 SSD1309_OFFSET_17,
883 SSD1309_OFFSET_18,
884 SSD1309_OFFSET_19,
885 SSD1309_OFFSET_20,
886 SSD1309_OFFSET_21,
887 SSD1309_OFFSET_22,
888 SSD1309_OFFSET_23,
889 SSD1309_OFFSET_24,
890 SSD1309_OFFSET_25,
891 SSD1309_OFFSET_26,
892 SSD1309_OFFSET_27,
893 SSD1309_OFFSET_28,
894 SSD1309_OFFSET_29,
895 SSD1309_OFFSET_30,
896 SSD1309_OFFSET_31,
897 SSD1309_OFFSET_32,
898 SSD1309_OFFSET_33,
899 SSD1309_OFFSET_34,
900 SSD1309_OFFSET_35,
901 SSD1309_OFFSET_36,
902 SSD1309_OFFSET_37,
903 SSD1309_OFFSET_38,
904 SSD1309_OFFSET_39,
905 SSD1309_OFFSET_40,
906 SSD1309_OFFSET_41,
907 SSD1309_OFFSET_42,
908 SSD1309_OFFSET_43,
909 SSD1309_OFFSET_44,
910 SSD1309_OFFSET_45,
911 SSD1309_OFFSET_46,
912 SSD1309_OFFSET_47,
913 SSD1309_OFFSET_48,
914 SSD1309_OFFSET_49,
915 SSD1309_OFFSET_50,
916 SSD1309_OFFSET_51,
917 SSD1309_OFFSET_52,
918 SSD1309_OFFSET_53,
919 SSD1309_OFFSET_54,
920 SSD1309_OFFSET_55,
921 SSD1309_OFFSET_56,
922 SSD1309_OFFSET_57,
923 SSD1309_OFFSET_58,
924 SSD1309_OFFSET_59,
925 SSD1309_OFFSET_60,
926 SSD1309_OFFSET_61,
927 SSD1309_OFFSET_62,
928 SSD1309_OFFSET_63
929}SSD1309_OFFSET_te;
930
935typedef enum {
936 SSD1309_CLK_DIV_RATIO_1 = 1,
937 SSD1309_CLK_DIV_RATIO_2,
938 SSD1309_CLK_DIV_RATIO_3,
939 SSD1309_CLK_DIV_RATIO_4,
940 SSD1309_CLK_DIV_RATIO_5,
941 SSD1309_CLK_DIV_RATIO_6,
942 SSD1309_CLK_DIV_RATIO_7,
943 SSD1309_CLK_DIV_RATIO_8,
944 SSD1309_CLK_DIV_RATIO_9,
945 SSD1309_CLK_DIV_RATIO_10,
946 SSD1309_CLK_DIV_RATIO_11,
947 SSD1309_CLK_DIV_RATIO_12,
948 SSD1309_CLK_DIV_RATIO_13,
949 SSD1309_CLK_DIV_RATIO_14,
950 SSD1309_CLK_DIV_RATIO_15,
951 SSD1309_CLK_DIV_RATIO_16
952}SSD1309_CLK_DIV_RATIO_te;
953
958typedef enum {
959 SSD1309_CLK_SPEED_LVL_0,
960 SSD1309_CLK_SPEED_LVL_LVL_1,
961 SSD1309_CLK_SPEED_LVL_LVL_2,
962 SSD1309_CLK_SPEED_LVL_LVL_3,
963 SSD1309_CLK_SPEED_LVL_LVL_4,
964 SSD1309_CLK_SPEED_LVL_LVL_5,
965 SSD1309_CLK_SPEED_LVL_LVL_6,
966 SSD1309_CLK_SPEED_LVL_LVL_7,
967 SSD1309_CLK_SPEED_LVL_LVL_8,
968 SSD1309_CLK_SPEED_LVL_LVL_9,
969 SSD1309_CLK_SPEED_LVL_LVL_10,
970 SSD1309_CLK_SPEED_LVL_LVL_11,
971 SSD1309_CLK_SPEED_LVL_LVL_12,
972 SSD1309_CLK_SPEED_LVL_LVL_13,
973 SSD1309_CLK_SPEED_LVL_LVL_14,
974 SSD1309_CLK_SPEED_LVL_LVL_15
975}SSD1309_CLK_SPEED_LVL_te;
976
981typedef enum {
982 SSD1309_PHASE1_PRECHARGE_DCLK_1 = 1,
983 SSD1309_PHASE1_PRECHARGE_DCLK_2,
984 SSD1309_PHASE1_PRECHARGE_DCLK_3,
985 SSD1309_PHASE1_PRECHARGE_DCLK_4,
986 SSD1309_PHASE1_PRECHARGE_DCLK_5,
987 SSD1309_PHASE1_PRECHARGE_DCLK_6,
988 SSD1309_PHASE1_PRECHARGE_DCLK_7,
989 SSD1309_PHASE1_PRECHARGE_DCLK_8,
990 SSD1309_PHASE1_PRECHARGE_DCLK_9,
991 SSD1309_PHASE1_PRECHARGE_DCLK_10,
992 SSD1309_PHASE1_PRECHARGE_DCLK_11,
993 SSD1309_PHASE1_PRECHARGE_DCLK_12,
994 SSD1309_PHASE1_PRECHARGE_DCLK_13,
995 SSD1309_PHASE1_PRECHARGE_DCLK_14,
996 SSD1309_PHASE1_PRECHARGE_DCLK_15
997}SSD1309_PHASE1_PRECHARGE_DCLK_te;
998
1003typedef enum {
1004 SSD1309_PHASE2_PRECHARGE_DCLK_1 = 1,
1005 SSD1309_PHASE2_PRECHARGE_DCLK_2,
1006 SSD1309_PHASE2_PRECHARGE_DCLK_3,
1007 SSD1309_PHASE2_PRECHARGE_DCLK_4,
1008 SSD1309_PHASE2_PRECHARGE_DCLK_5,
1009 SSD1309_PHASE2_PRECHARGE_DCLK_6,
1010 SSD1309_PHASE2_PRECHARGE_DCLK_7,
1011 SSD1309_PHASE2_PRECHARGE_DCLK_8,
1012 SSD1309_PHASE2_PRECHARGE_DCLK_9,
1013 SSD1309_PHASE2_PRECHARGE_DCLK_10,
1014 SSD1309_PHASE2_PRECHARGE_DCLK_11,
1015 SSD1309_PHASE2_PRECHARGE_DCLK_12,
1016 SSD1309_PHASE2_PRECHARGE_DCLK_13,
1017 SSD1309_PHASE2_PRECHARGE_DCLK_14,
1018 SSD1309_PHASE2_PRECHARGE_DCLK_15
1019}SSD1309_PHASE2_PRECHARGE_DCLK_te;
1020
1027typedef enum {
1028 SSD1309_VCOMH_DESELECT_LVL_LOW,
1029 SSD1309_VCOMH_DESELECT_LVL_MED = 13,
1030 SSD1309_VCOMH_DESELECT_LVL_HIGH = 15
1031}SSD1309_VCOMH_DESELECT_LVL_te;
1032
1125
1136typedef struct ssd1309_handle_s SSD1309_HANDLE_ts;
1137
1139
1146
1161ERR_te ssd1309_init_subsys(void);
1162
1175ERR_te ssd1309_deinit_subsys(void);
1176
1184ERR_te ssd1309_start_subsys(void);
1185
1193ERR_te ssd1309_stop_subsys(void);
1194
1214ERR_te ssd1309_get_def_cfg(SSD1309_CFG_ts *ssd1309_cfg_o);
1215
1238ERR_te ssd1309_init_handle(SSD1309_CFG_ts *ssd1309_cfg, SSD1309_HANDLE_ts **ssd1309_handle_o);
1239
1261ERR_te ssd1309_draw_text(char const *text, uint8_t text_len, uint8_t line, bool force);
1262
1282ERR_te ssd1309_draw_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force);
1283
1299ERR_te ssd1309_clear_line(uint8_t line, bool force);
1300
1317ERR_te ssd1309_invert_line(uint8_t line, bool force);
1318
1338ERR_te ssd1309_clear_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force);
1339
1359ERR_te ssd1309_invert_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force);
1360
1374ERR_te ssd1309_update(bool force);
1375
1377
1378#endif
1379
err.h
System-wide error code definitions.
ERR_te
ERR_te
Standard return type used by all public API functions.
Definition err.h:35
ssd1309_update
ERR_te ssd1309_update(bool force)
Flushes the internal framebuffer to the display over I2C.
Definition ssd1309.c:1064
ssd1309_deinit_subsys
ERR_te ssd1309_deinit_subsys(void)
Deinitializes the SSD1309 subsystem.
Definition ssd1309.c:523
ssd1309_init_handle
ERR_te ssd1309_init_handle(SSD1309_CFG_ts *ssd1309_cfg, SSD1309_HANDLE_ts **ssd1309_handle_o)
Initializes the SSD1309 display and sends the full configuration sequence over I2C.
Definition ssd1309.c:622
ssd1309_draw_rect
ERR_te ssd1309_draw_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force)
Draws a filled rectangle into the framebuffer.
Definition ssd1309.c:843
ssd1309_invert_line
ERR_te ssd1309_invert_line(uint8_t line, bool force)
Inverts all pixels in a single display line in the framebuffer.
Definition ssd1309.c:924
ssd1309_init_subsys
ERR_te ssd1309_init_subsys(void)
Initializes the SSD1309 subsystem.
Definition ssd1309.c:488
ssd1309_start_subsys
ERR_te ssd1309_start_subsys(void)
Starts the SSD1309 subsystem.
Definition ssd1309.c:551
ssd1309_clear_rect
ERR_te ssd1309_clear_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force)
Clears a rectangular region in the framebuffer (sets all pixels off).
Definition ssd1309.c:947
ssd1309_draw_text
ERR_te ssd1309_draw_text(char const *text, uint8_t text_len, uint8_t line, bool force)
Draws a text string into the framebuffer at the specified line.
Definition ssd1309.c:806
ssd1309_get_def_cfg
ERR_te ssd1309_get_def_cfg(SSD1309_CFG_ts *ssd1309_cfg_o)
Populates a configuration structure with sensible default values.
Definition ssd1309.c:599
ssd1309_invert_rect
ERR_te ssd1309_invert_rect(uint8_t x_src, uint8_t y_src, uint8_t x_dest, uint8_t y_dest, bool force)
Inverts all pixels in a rectangular region of the framebuffer.
Definition ssd1309.c:1005
ssd1309_stop_subsys
ERR_te ssd1309_stop_subsys(void)
Stops the SSD1309 subsystem.
Definition ssd1309.c:575
ssd1309_clear_line
ERR_te ssd1309_clear_line(uint8_t line, bool force)
Clears a single display line in the framebuffer (sets all pixels off).
Definition ssd1309.c:901
SSD1309_VERTICAL_FLIP_te
SSD1309_VERTICAL_FLIP_te
Flip the image vertically.
Definition ssd1309.h:855
SSD1309_CLK_SPEED_LVL_te
SSD1309_CLK_SPEED_LVL_te
The clock speed of the SSD1309.
Definition ssd1309.h:958
SSD1309_PHASE2_PRECHARGE_DCLK_te
SSD1309_PHASE2_PRECHARGE_DCLK_te
Phase 2 (charge) length of the segment (pixel) output wave form.
Definition ssd1309.h:1003
SSD1309_COL_ADDR_START_HAM_VAM_te
SSD1309_COL_ADDR_START_HAM_VAM_te
Column start address for RAM scanning of the SSD1309. Only relevant for HAM and VAM.
Definition ssd1309.h:132
SSD1309_PAGE_START_ADDR_PAM_te
SSD1309_PAGE_START_ADDR_PAM_te
Page address start for RAM scanning of the SSD1309. Only relevant for PAM.
Definition ssd1309.h:840
SSD1309_MEM_ADDR_MODE_te
SSD1309_MEM_ADDR_MODE_te
Memory addressing mode:
Definition ssd1309.h:122
SSD1309_HANDLE_ts
struct ssd1309_handle_s SSD1309_HANDLE_ts
Opaque handle representing an SSD1309 display instance.
Definition ssd1309.h:1136
SSD1309_VCOMH_DESELECT_LVL_te
SSD1309_VCOMH_DESELECT_LVL_te
The deselect level of a LED row in the SSD1309. LOW -> 0.64 * Vcc MED -> 0.78 * Vcc HIGH -> 0....
Definition ssd1309.h:1027
SSD1309_COL_ADDR_END_HAM_VAM_te
SSD1309_COL_ADDR_END_HAM_VAM_te
Column end address for RAM scanning of the SSD1309. Only relevant for HAM and VAM.
Definition ssd1309.h:267
SSD1309_CONTRAST_te
SSD1309_CONTRAST_te
Current control (brightness) of the LEDs in the SSD1309.
Definition ssd1309.h:503
SSD1309_INVERSE_MODE_te
SSD1309_INVERSE_MODE_te
Causes the values stored in RAM to have the opposite effect. (1 to turn off pixel,...
Definition ssd1309.h:775
SSD1309_CLK_DIV_RATIO_te
SSD1309_CLK_DIV_RATIO_te
The divide ratio of the SSD1309 clock.
Definition ssd1309.h:935
SSD1309_PAGE_ADDR_END_HAM_VAM_te
SSD1309_PAGE_ADDR_END_HAM_VAM_te
Page address end for RAM scanning of the SSD1309. Only relevant for HAM and VAM.
Definition ssd1309.h:417
SSD1309_PAGE_ADDR_START_HAM_VAM_te
SSD1309_PAGE_ADDR_START_HAM_VAM_te
Page address start for RAM scanning of the SSD1309. Only relevant for HAM and VAM.
Definition ssd1309.h:402
SSD1309_MULTIPLEX_RATIO_te
SSD1309_MULTIPLEX_RATIO_te
Number of SSD1309 LED lines activated.
Definition ssd1309.h:784
SSD1309_HORIZONTAL_FLIP_te
SSD1309_HORIZONTAL_FLIP_te
Flip the image horizontally.
Definition ssd1309.h:766
SSD1309_HIGH_COL_START_ADDR_PAM_te
SSD1309_HIGH_COL_START_ADDR_PAM_te
Higher column start address (upper 4 bit part of 8 bit address) for RAM scanning of the SSD1309....
Definition ssd1309.h:105
SSD1309_START_LINE_te
SSD1309_START_LINE_te
Which row in RAM to appear at the top of the screen.
Definition ssd1309.h:432
SSD1309_OFFSET_te
SSD1309_OFFSET_te
selects which RAM row is internally linked to COM0.
Definition ssd1309.h:864
SSD1309_PHASE1_PRECHARGE_DCLK_te
SSD1309_PHASE1_PRECHARGE_DCLK_te
Phase 1 (discharge) length of the segment (pixel) output wave form.
Definition ssd1309.h:981
SSD1309_LOW_COL_START_ADDR_PAM_te
SSD1309_LOW_COL_START_ADDR_PAM_te
Lower column start address (lower 4 bit part of 8 bit address) for RAM scanning of the SSD1309....
Definition ssd1309.h:81
GPIO_PIN_te
GPIO_PIN_te
GPIO pin number within a port (0–15).
Definition stm32f401re_gpio.h:50
GPIO_ALTERNATE_FUNCTION_te
GPIO_ALTERNATE_FUNCTION_te
GPIO alternate function mapping (AF0–AF15).
Definition stm32f401re_gpio.h:126
stm32f401re.h
STM32F401RE MCU-specific peripheral register definitions and bit position enumerations.
stm32f401re_gpio.h
STM32F401RE GPIO driver public API.
GPIO_REGDEF_ts
GPIO peripheral register map.
Definition stm32f401re.h:95
I2C_REGDEF_ts
I2C peripheral register map.
Definition stm32f401re.h:241
SSD1309_CFG_ts
Full configuration structure for initializing an SSD1309 display handle.
Definition ssd1309.h:1046
SSD1309_CFG_ts::scl_gpio_pin
GPIO_PIN_te scl_gpio_pin
Definition ssd1309.h:1054
SSD1309_CFG_ts::phase2_precharge_dclk
SSD1309_PHASE2_PRECHARGE_DCLK_te phase2_precharge_dclk
Definition ssd1309.h:1120
SSD1309_CFG_ts::page_start_addr_pam
SSD1309_PAGE_START_ADDR_PAM_te page_start_addr_pam
Definition ssd1309.h:1102
SSD1309_CFG_ts::page_addr_end_ham_vam
SSD1309_PAGE_ADDR_END_HAM_VAM_te page_addr_end_ham_vam
Definition ssd1309.h:1084
SSD1309_CFG_ts::high_col_start_addr_pam
SSD1309_HIGH_COL_START_ADDR_PAM_te high_col_start_addr_pam
Definition ssd1309.h:1069
SSD1309_CFG_ts::mem_addr_mode
SSD1309_MEM_ADDR_MODE_te mem_addr_mode
Definition ssd1309.h:1072
SSD1309_CFG_ts::multiplex_ratio
SSD1309_MULTIPLEX_RATIO_te multiplex_ratio
Definition ssd1309.h:1099
SSD1309_CFG_ts::low_col_start_addr_pam
SSD1309_LOW_COL_START_ADDR_PAM_te low_col_start_addr_pam
Definition ssd1309.h:1066
SSD1309_CFG_ts::page_addr_start_ham_vam
SSD1309_PAGE_ADDR_START_HAM_VAM_te page_addr_start_ham_vam
Definition ssd1309.h:1081
SSD1309_CFG_ts::vcomh_deselect_lvl
SSD1309_VCOMH_DESELECT_LVL_te vcomh_deselect_lvl
Definition ssd1309.h:1123
SSD1309_CFG_ts::clk_speed_lvl
SSD1309_CLK_SPEED_LVL_te clk_speed_lvl
Definition ssd1309.h:1114
SSD1309_CFG_ts::start_line
SSD1309_START_LINE_te start_line
Definition ssd1309.h:1087
SSD1309_CFG_ts::gpio_alternate_function
GPIO_ALTERNATE_FUNCTION_te gpio_alternate_function
Definition ssd1309.h:1063
SSD1309_CFG_ts::i2c_instance
I2C_REGDEF_ts * i2c_instance
Definition ssd1309.h:1048
SSD1309_CFG_ts::scl_gpio_port
GPIO_REGDEF_ts * scl_gpio_port
Definition ssd1309.h:1051
SSD1309_CFG_ts::horizontal_flip
SSD1309_HORIZONTAL_FLIP_te horizontal_flip
Definition ssd1309.h:1093
SSD1309_CFG_ts::contrast
SSD1309_CONTRAST_te contrast
Definition ssd1309.h:1090
SSD1309_CFG_ts::sda_gpio_port
GPIO_REGDEF_ts * sda_gpio_port
Definition ssd1309.h:1057
SSD1309_CFG_ts::sda_gpio_pin
GPIO_PIN_te sda_gpio_pin
Definition ssd1309.h:1060
SSD1309_CFG_ts::offset
SSD1309_OFFSET_te offset
Definition ssd1309.h:1108
SSD1309_CFG_ts::phase1_precharge_dclk
SSD1309_PHASE1_PRECHARGE_DCLK_te phase1_precharge_dclk
Definition ssd1309.h:1117
SSD1309_CFG_ts::col_addr_start_ham_vam
SSD1309_COL_ADDR_START_HAM_VAM_te col_addr_start_ham_vam
Definition ssd1309.h:1075
SSD1309_CFG_ts::clk_div_ratio
SSD1309_CLK_DIV_RATIO_te clk_div_ratio
Definition ssd1309.h:1111
SSD1309_CFG_ts::vertical_flip
SSD1309_VERTICAL_FLIP_te vertical_flip
Definition ssd1309.h:1105
SSD1309_CFG_ts::col_addr_end_ham_vam
SSD1309_COL_ADDR_END_HAM_VAM_te col_addr_end_ham_vam
Definition ssd1309.h:1078
SSD1309_CFG_ts::inverse_mode
SSD1309_INVERSE_MODE_te inverse_mode
Definition ssd1309.h:1096
ssd1309_handle_s
Internal structure representing the SSD1309 hardware instance.
Definition ssd1309.c:345