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GPS Device
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I2C peripheral register map. More...
#include <stm32f401re.h>
Public Attributes | |
| uint32_t volatile | I2C_CR1 |
| uint32_t volatile | I2C_CR2 |
| uint32_t volatile | I2C_OAR1 |
| uint32_t volatile | I2C_OAR2 |
| uint32_t volatile | I2C_DR |
| uint32_t volatile | I2C_SR1 |
| uint32_t volatile | I2C_SR2 |
| uint32_t volatile | I2C_CCR |
| uint32_t volatile | I2C_TRISE |
| uint32_t volatile | I2C_FLTR |
I2C peripheral register map.
Instantiated via the I2C1, I2C2, I2C3 accessor macros.
Definition at line 241 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_CR1 |
Control register 1: PE, START, STOP, ACK, clock stretch.
Definition at line 242 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_CR2 |
Control register 2: FREQ field (APB1 MHz), interrupt and DMA enables.
Definition at line 243 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_OAR1 |
Own address register 1: 7-bit or 10-bit own address.
Definition at line 244 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_OAR2 |
Own address register 2: dual-address mode.
Definition at line 245 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_DR |
Data register: write to transmit, read to receive.
Definition at line 246 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_SR1 |
Status register 1: SB, ADDR, TxE, RxNE, BTF, error flags.
Definition at line 247 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_SR2 |
Status register 2: MSL, BUSY, TRA flags; reading clears ADDR.
Definition at line 248 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_CCR |
Clock control register: CCR value, DUTY, FS (standard/fast mode).
Definition at line 249 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_TRISE |
TRISE register: maximum rise time in units of 1/APB1 clock.
Definition at line 250 of file stm32f401re.h.
| uint32_t volatile I2C_REGDEF_ts::I2C_FLTR |
Filter register: analog and digital noise filters.
Definition at line 251 of file stm32f401re.h.