STM32F401RE Hardware Abstraction Layer

Peripheral register definitions and bit positions for the STM32F401RE. More...

Collaboration diagram for STM32F401RE Hardware Abstraction Layer:

Topics
	Peripheral Base Addresses
	Memory-mapped base addresses for all STM32F401RE peripherals.
	Peripheral Register Definitions
	Memory-mapped register structures for STM32F401RE peripherals.
	Register Bit Positions
	Bit position enumerations for STM32F401RE peripheral registers.
	Peripheral Accessor Macros
	Pointer-cast macros for accessing peripheral register maps by name.
	IRQ Numbers and EXTI Lines
	IRQ position enumeration and EXTI line definitions.
	Legacy GPIO Clock Macros
	Convenience macros for GPIO peripheral clock enable/disable.

Detailed Description

Peripheral register definitions and bit positions for the STM32F401RE.