Register Bit Positions

Bit position enumerations for STM32F401RE peripheral registers. More...

Collaboration diagram for Register Bit Positions:

Enumerations
enum	APB1ENR_te { APB1ENR_PWREN = 28 }
	APB1ENR register bit positions (legacy, prefer RCC_APB1ENR_te). More...
enum	PWR_CR_te { PWR_CR_DBP = 8 }
	PWR_CR register bit positions. More...
enum	RCC_CR_te { RCC_CR_HSEON = 16 , RCC_CR_HSERDY = 17 }
	RCC_CR register bit positions. More...
enum	RCC_BDCR_te {   RCC_BDCR_LSEON = 0 , RCC_BDCR_LSERDY = 1 , RCC_BDCR_LSEBYP = 2 , RCC_BDCR_RTCSEL = 8 ,   RCC_BDCR_RTCEN = 15 , RCC_BDCR_BDRST = 16 }
	RCC_BDCR register bit positions. More...
enum	RCC_CSR_te { RCC_CSR_LSION = 0 , RCC_CSR_LSIRDY = 1 }
	RCC_CSR register bit positions. More...
enum	RTC_CR_te { RTC_CR_FMT = 6 }
	RTC_CR register bit positions. More...
enum	RTC_ISR_te { RTC_ISR_RSF = 5 , RTC_ISR_INITF = 6 , RTC_ISR_INIT = 7 }
	RTC_ISR register bit positions. More...
enum	RTC_TR_te {   RTC_TR_SU = 0 , RTC_TR_ST = 4 , RTC_TR_MNU = 8 , RTC_TR_MNT = 12 ,   RTC_TR_HU = 16 , RTC_TR_HT = 20 , RTC_TR_PM = 22 }
	RTC_TR register bit positions (all fields BCD-encoded). More...
enum	RTC_DR_te {   RTC_DR_DU = 0 , RTC_DR_DT = 4 , RTC_DR_MU = 8 , RTC_DR_MT = 12 ,   RTC_DR_WDU = 13 , RTC_DR_YU = 16 , RTC_DR_YT = 20 }
	RTC_DR register bit positions (all fields BCD-encoded). More...
enum	RTC_PRER_te { RTC_PRER_PREDIV_S = 0 , RTC_PRER_PREDIV_A = 16 }
	RTC_PRER register bit positions. More...
enum	SPI_CR1_te {   SPI_CR1_CPHA = 0 , SPI_CR1_CPOL = 1 , SPI_CR1_MSTR = 2 , SPI_CR1_BR = 3 ,   SPI_CR1_SPE = 6 , SPI_CR1_LSBFIRST = 7 , SPI_CR1_SSI = 8 , SPI_CR1_SSM = 9 ,   SPI_CR1_RXONLY = 10 , SPI_CR1_DFF = 11 , SPI_CR1_CRCNEXT = 12 , SPI_CR1_CRCEN = 13 ,   SPI_CR1_BIDIOE = 14 , SPI_CR1_BIDIMODE = 15 }
	SPI_CR1 register bit positions. More...
enum	SPI_CR2_te {   SPI_CR2_RXDMAEN = 0 , SPI_CR2_TXDMAEN = 1 , SPI_CR2_SSOE = 2 , SPI_CR2_FRF = 4 ,   SPI_CR2_ERRIE = 5 , SPI_CR2_RXNEIE = 6 , SPI_CR2_TXEIE = 7 }
	SPI_CR2 register bit positions. More...
enum	SPI_SR_te {   SPI_SR_RXNE = 0 , SPI_SR_TXE = 1 , SPI_SR_CHSIDE = 2 , SPI_SR_UDR = 3 ,   SPI_SR_CRCERR = 4 , SPI_SR_MODF = 5 , SPI_SR_OVR = 6 , SPI_SR_BSY = 7 ,   SPI_SR_FRE = 8 }
	SPI_SR register bit positions. More...
enum	RCC_CFGR_te { RCC_CFGR_SWS = 2 , RCC_CFGR_HPRE = 4 , RCC_CFGR_PPRE1 = 10 , RCC_CFGR_PPRE2 = 13 }
	RCC_CFGR register bit positions. More...
enum	I2C_CR1_te {   I2C_CR1_PE = 0 , I2C_CR1_SMBUS = 1 , I2C_CR1_SMBTYPE = 3 , I2C_CR1_ENARP = 4 ,   I2C_CR1_ENPEC = 5 , I2C_CR1_ENGC = 6 , I2C_CR1_NOSTRETCH = 7 , I2C_CR1_START = 8 ,   I2C_CR1_STOP = 9 , I2C_CR1_ACK = 10 , I2C_CR1_POS = 11 , I2C_CR1_PEC = 12 ,   I2C_CR1_ALERT = 13 , I2C_CR1_SWRST = 15 }
	I2C_CR1 register bit positions. More...
enum	I2C_CR2_te {   I2C_CR2_FREQ = 0 , I2C_CR2_ITERREN = 8 , I2C_CR2_ITEVTEN = 9 , I2C_CR2_ITBUFEN = 10 ,   I2C_CR2_DMAEN = 11 , I2C_CR2_LAST = 12 }
	I2C_CR2 register bit positions. More...
enum	I2C_SR1_te {   I2C_SR1_SB = 0 , I2C_SR1_ADDR = 1 , I2C_SR1_BTF = 2 , I2C_SR1_ADD10 = 3 ,   I2C_SR1_STOPF = 4 , I2C_SR1_RxNE = 6 , I2C_SR1_TxE = 7 , I2C_SR1_BERR = 8 ,   I2C_SR1_ARLO = 9 , I2C_SR1_AF = 10 , I2C_SR1_OVR = 11 , I2C_SR1_PECERR = 12 ,   I2C_SR1_TIMEOUT = 14 , I2C_SR1_SMBALERT = 15 }
	I2C_SR1 register bit positions. More...
enum	I2C_SR2_te {   I2C_SR2_MSL = 0 , I2C_SR2_BUSY = 1 , I2C_SR2_TRA = 2 , I2C_SR2_GENCALL = 4 ,   I2C_SR2_SMBDEFAULT = 5 , I2C_SR2_SMBHOST = 6 , I2C_SR2_DUALF = 7 , I2C_SR2_PEC = 8 }
	I2C_SR2 register bit positions. More...
enum	I2C_CCR_te { I2C_CCR_CCR = 0 , I2C_CCR_DUTY = 14 , I2C_CCR_FS = 15 }
	I2C_CCR register bit positions. More...
enum	I2C_OAR1_te { I2C_OAR1_ADD0 = 0 , I2C_OAR1_ADD7_1 = 1 , I2C_OAR1_ADD9_8 = 8 , I2C_OAR1_ADDMODE = 15 }
	I2C_OAR1 register bit positions. More...
enum	USART_SR_te {   USART_SR_PE = 0 , USART_SR_FE = 1 , USART_SR_NF = 2 , USART_SR_ORE = 3 ,   USART_SR_IDLE = 4 , USART_SR_RXNE = 5 , USART_SR_TC = 6 , USART_SR_TXE = 7 ,   USART_SR_LBD = 8 , USART_SR_CTS = 9 }
	USART_SR register bit positions. More...
enum	USART_BRR_te { USART_BRR_DIV_FRACTION = 0 , USART_BRR_DIV_MANTISSA = 4 }
	USART_BRR register bit positions. More...
enum	USART_CR1_te {   USART_CR1_SBK = 0 , USART_CR1_RWU = 1 , USART_CR1_RE = 2 , USART_CR1_TE = 3 ,   USART_CR1_IDLEIE = 4 , USART_CR1_RXNEIE = 5 , USART_CR1_TCIE = 6 , USART_CR1_TXEIE = 7 ,   USART_CR1_PEIE = 8 , USART_CR1_PS = 9 , USART_CR1_PCE = 10 , USART_CR1_WAKE = 11 ,   USART_CR1_M = 12 , USART_CR1_UE = 13 , USART_CR1_OVER8 = 15 }
	USART_CR1 register bit positions. More...
enum	USART_CR2_te {   USART_CR2_ADD = 0 , USART_CR2_LBDL = 5 , USART_CR2_LBDIE = 6 , USART_CR2_LBCL = 8 ,   USART_CR2_CPHA = 9 , USART_CR2_CPOL = 10 , USART_CR2_CLKEN = 11 , USART_CR2_STOP = 12 ,   USART_CR2_LINEN = 14 }
	USART_CR2 register bit positions. More...
enum	USART_CR3_te {   USART_CR3_EIE = 0 , USART_CR3_IREN = 1 , USART_CR3_IRLP = 2 , USART_CR3_HDSEL = 3 ,   USART_CR3_NACK = 4 , USART_CR3_SCEN = 5 , USART_CR3_DMAR = 6 , USART_CR3_DMAT = 7 ,   USART_CR3_RTSE = 8 , USART_CR3_CTSE = 9 , USART_CR3_CTSIE = 10 , USART_CR3_ONEBIT = 11 }
	USART_CR3 register bit positions. More...
enum	RCC_AHB1ENR_te {   RCC_AHB1ENR_GPIOAEN = 0 , RCC_AHB1ENR_GPIOBEN = 1 , RCC_AHB1ENR_GPIOCEN = 2 , RCC_AHB1ENR_GPIODEN = 3 ,   RCC_AHB1ENR_GPIOEEN = 4 , RCC_AHB1ENR_GPIOHEN = 7 , RCC_AHB1ENR_CRCEN = 12 , RCC_AHB1ENR_DMA1EN = 21 ,   RCC_AHB1ENR_DMA2EN = 22 }
	RCC_AHB1ENR register bit positions. More...
enum	RCC_AHB1RSTR_te {   RCC_AHB1RSTR_GPIOARST = 0 , RCC_AHB1RSTR_GPIOBRST = 1 , RCC_AHB1RSTR_GPIOCRST = 2 , RCC_AHB1RSTR_GPIODRST = 3 ,   RCC_AHB1RSTR_GPIOERST = 4 , RCC_AHB1RSTR_GPIOHRST = 7 , RCC_AHB1RSTR_CRCRST = 12 , RCC_AHB1RSTR_DMA1RST = 21 ,   RCC_AHB1RSTR_DMA2RST = 22 }
	RCC_AHB1RSTR register bit positions. More...
enum	RCC_APB1ENR_te {   RCC_APB1ENR_TIM2EN = 0 , RCC_APB1ENR_TIM3EN = 1 , RCC_APB1ENR_TIM4EN = 2 , RCC_APB1ENR_TIM5EN = 3 ,   RCC_APB1ENR_WWDGEN = 11 , RCC_APB1ENR_SPI2EN = 14 , RCC_APB1ENR_SPI3EN = 15 , RCC_APB1ENR_USART2EN = 17 ,   RCC_APB1ENR_I2C1EN = 21 , RCC_APB1ENR_I2C2EN = 22 , RCC_APB1ENR_I2C3EN = 23 , RCC_APB1ENR_PWREN = 28 }
	RCC_APB1ENR register bit positions. More...
enum	RCC_APB1RSTR_te {   RCC_APB1RSTR_TIM2RST = 0 , RCC_APB1RSTR_TIM3RST = 1 , RCC_APB1RSTR_TIM4RST = 2 , RCC_APB1RSTR_TIM5RST = 3 ,   RCC_APB1RSTR_WWDGRST = 11 , RCC_APB1RSTR_SPI2RST = 14 , RCC_APB1RSTR_SPI3RST = 15 , RCC_APB1RSTR_USART2RST = 17 ,   RCC_APB1RSTR_I2C1RST = 21 , RCC_APB1RSTR_I2C2RST = 22 , RCC_APB1RSTR_I2C3RST = 23 , RCC_APB1RSTR_PWRRST = 28 }
	RCC_APB1RSTR register bit positions. More...
enum	RCC_APB2ENR_te {   RCC_APB2ENR_TIM1EN = 0 , RCC_APB2ENR_USART1EN = 4 , RCC_APB2ENR_USART6EN = 5 , RCC_APB2ENR_ADC1EN = 8 ,   RCC_APB2ENR_SDIOEN = 11 , RCC_APB2ENR_SPI1EN = 12 , RCC_APB2ENR_SPI4EN = 13 , RCC_APB2ENR_SYSCFGEN = 14 ,   RCC_APB2ENR_TIM9EN = 16 , RCC_APB2ENR_TIM10EN = 17 , RCC_APB2ENR_TIM11EN = 18 }
	RCC_APB2ENR register bit positions. More...
enum	RCC_APB2RSTR_te {   RCC_APB2RSTR_TIM1RST = 0 , RCC_APB2RSTR_USART1RST = 4 , RCC_APB2RSTR_USART6RST = 5 , RCC_APB2RSTR_ADC1RST = 8 ,   RCC_APB2RSTR_SDIORST = 11 , RCC_APB2RSTR_SPI1RST = 12 , RCC_APB2RSTR_SPI4RST = 13 , RCC_APB2RSTR_SYSCFGRST = 14 ,   RCC_APB2RSTR_TIM9RST = 16 , RCC_APB2RSTR_TIM10RST = 17 , RCC_APB2RSTR_TIM11RST = 18 }
	RCC_APB2RSTR register bit positions. More...

Detailed Description

Bit position enumerations for STM32F401RE peripheral registers.

Each enumerator value is a bit position (not a mask) for use with the shift-and-mask pattern: (reg >> BIT_POS) & mask.

Enumeration Type Documentation

APB1ENR_te

enum APB1ENR_te

APB1ENR register bit positions (legacy, prefer RCC_APB1ENR_te).

Enumerator
APB1ENR_PWREN	Bit 28: Power interface clock enable.

Definition at line 286 of file stm32f401re.h.

{
    APB1ENR_PWREN = 28 
} APB1ENR_te;

PWR_CR_te

enum PWR_CR_te

PWR_CR register bit positions.

Enumerator
PWR_CR_DBP	Bit 8: Disable backup domain write protection. Must be set before writing RTC/backup registers.

Definition at line 294 of file stm32f401re.h.

{
    PWR_CR_DBP = 8 
} PWR_CR_te;

RCC_CR_te

enum RCC_CR_te

RCC_CR register bit positions.

Enumerator
RCC_CR_HSEON	Bit 16: HSE oscillator enable.
RCC_CR_HSERDY	Bit 17: HSE oscillator ready flag (read-only).

Definition at line 302 of file stm32f401re.h.

{
    RCC_CR_HSEON  = 16, 
    RCC_CR_HSERDY = 17  
} RCC_CR_te;

RCC_BDCR_te

enum RCC_BDCR_te

RCC_BDCR register bit positions.

Enumerator
RCC_BDCR_LSEON	Bit 0: LSE oscillator enable.
RCC_BDCR_LSERDY	Bit 1: LSE oscillator ready flag (read-only).
RCC_BDCR_LSEBYP	Bit 2: LSE oscillator bypass (for external clock input).
RCC_BDCR_RTCSEL	Bits 9:8: RTC clock source selection (1 = LSE, 2 = LSI, 3 = HSE/div).
RCC_BDCR_RTCEN	Bit 15: RTC clock enable.
RCC_BDCR_BDRST	Bit 16: Backup domain software reset. Clears RTC and backup registers.

Definition at line 311 of file stm32f401re.h.

{
    RCC_BDCR_LSEON  = 0,  
    RCC_BDCR_LSERDY = 1,  
    RCC_BDCR_LSEBYP = 2,  
    RCC_BDCR_RTCSEL = 8,  
    RCC_BDCR_RTCEN  = 15, 
    RCC_BDCR_BDRST  = 16  
} RCC_BDCR_te;

RCC_CSR_te

enum RCC_CSR_te

RCC_CSR register bit positions.

Enumerator
RCC_CSR_LSION	Bit 0: LSI oscillator enable.
RCC_CSR_LSIRDY	Bit 1: LSI oscillator ready flag (read-only).

Definition at line 324 of file stm32f401re.h.

{
    RCC_CSR_LSION  = 0, 
    RCC_CSR_LSIRDY = 1  
} RCC_CSR_te;

RTC_CR_te

enum RTC_CR_te

RTC_CR register bit positions.

Enumerator
RTC_CR_FMT	Bit 6: Time format (0 = 24-hour, 1 = AM/PM).

Definition at line 333 of file stm32f401re.h.

{
    RTC_CR_FMT = 6 
} RTC_CR_te;

RTC_ISR_te

enum RTC_ISR_te

RTC_ISR register bit positions.

Enumerator
RTC_ISR_RSF	Bit 5: Registers synchronization flag. Set after TR/DR shadow regs are updated.
RTC_ISR_INITF	Bit 6: Initialization mode flag. Set when RTC is ready for initialization writes.
RTC_ISR_INIT	Bit 7: Initialization mode enable. Write 1 to enter, 0 to exit.

Definition at line 341 of file stm32f401re.h.

{
    RTC_ISR_RSF   = 5, 
    RTC_ISR_INITF = 6, 
    RTC_ISR_INIT  = 7  
} RTC_ISR_te;

RTC_TR_te

enum RTC_TR_te

RTC_TR register bit positions (all fields BCD-encoded).

Enumerator
RTC_TR_SU	Bits 3:0: Seconds units (0–9).
RTC_TR_ST	Bits 6:4: Seconds tens (0–5).
RTC_TR_MNU	Bits 11:8: Minutes units (0–9).
RTC_TR_MNT	Bits 14:12: Minutes tens (0–5).
RTC_TR_HU	Bits 19:16: Hours units (0–9).
RTC_TR_HT	Bits 21:20: Hours tens (0–2).
RTC_TR_PM	Bit 22: AM/PM notation (0 = AM, 1 = PM). Only relevant in 12-hour mode.

Definition at line 351 of file stm32f401re.h.

{
    RTC_TR_SU  = 0,  
    RTC_TR_ST  = 4,  
    RTC_TR_MNU = 8,  
    RTC_TR_MNT = 12, 
    RTC_TR_HU  = 16, 
    RTC_TR_HT  = 20, 
    RTC_TR_PM  = 22  
} RTC_TR_te;

RTC_DR_te

enum RTC_DR_te

RTC_DR register bit positions (all fields BCD-encoded).

Enumerator
RTC_DR_DU	Bits 3:0: Date units (1–9).
RTC_DR_DT	Bits 5:4: Date tens (0–3).
RTC_DR_MU	Bits 11:8: Month units (1–9).
RTC_DR_MT	Bit 12: Month tens (0 or 1).
RTC_DR_WDU	Bits 15:13: Weekday units (1 = Monday … 7 = Sunday).
RTC_DR_YU	Bits 19:16: Year units (0–9).
RTC_DR_YT	Bits 23:20: Year tens (0–9). Year is 2000 + (YT×10 + YU).

Definition at line 365 of file stm32f401re.h.

{
    RTC_DR_DU  = 0,  
    RTC_DR_DT  = 4,  
    RTC_DR_MU  = 8,  
    RTC_DR_MT  = 12, 
    RTC_DR_WDU = 13, 
    RTC_DR_YU  = 16, 
    RTC_DR_YT  = 20  
} RTC_DR_te;

RTC_PRER_te

enum RTC_PRER_te

RTC_PRER register bit positions.

Enumerator
RTC_PRER_PREDIV_S	Bits 14:0: Synchronous prescaler factor. f_ck_spre = f_ck_apre / (PREDIV_S + 1).
RTC_PRER_PREDIV_A	Bits 22:16: Asynchronous prescaler factor. f_ck_apre = LSE / (PREDIV_A + 1).

Definition at line 379 of file stm32f401re.h.

{
    RTC_PRER_PREDIV_S = 0,  
    RTC_PRER_PREDIV_A = 16  
} RTC_PRER_te;

SPI_CR1_te

enum SPI_CR1_te

SPI_CR1 register bit positions.

Enumerator
SPI_CR1_CPHA	Bit 0: Clock phase (0 = first edge, 1 = second edge).
SPI_CR1_CPOL	Bit 1: Clock polarity (0 = idle low, 1 = idle high).
SPI_CR1_MSTR	Bit 2: Master selection (0 = slave, 1 = master).
SPI_CR1_BR	Bits 5:3: Baud rate control (SCK = PCLK / 2^(BR+1)).
SPI_CR1_SPE	Bit 6: SPI enable.
SPI_CR1_LSBFIRST	Bit 7: Frame format (0 = MSB first, 1 = LSB first).
SPI_CR1_SSI	Bit 8: Internal slave select (must be 1 in master SW-NSS mode).
SPI_CR1_SSM	Bit 9: Software slave management (0 = HW NSS, 1 = SW NSS).
SPI_CR1_RXONLY	Bit 10: Receive-only mode.
SPI_CR1_DFF	Bit 11: Data frame format (0 = 8-bit, 1 = 16-bit).
SPI_CR1_CRCNEXT	Bit 12: Transmit CRC next.
SPI_CR1_CRCEN	Bit 13: Hardware CRC calculation enable.
SPI_CR1_BIDIOE	Bit 14: Bidirectional data mode output enable.
SPI_CR1_BIDIMODE	Bit 15: Bidirectional data mode enable.

Definition at line 388 of file stm32f401re.h.

{
    SPI_CR1_CPHA     = 0,  
    SPI_CR1_CPOL     = 1,  
    SPI_CR1_MSTR     = 2,  
    SPI_CR1_BR       = 3,  
    SPI_CR1_SPE      = 6,  
    SPI_CR1_LSBFIRST = 7,  
    SPI_CR1_SSI      = 8,  
    SPI_CR1_SSM      = 9,  
    SPI_CR1_RXONLY   = 10, 
    SPI_CR1_DFF      = 11, 
    SPI_CR1_CRCNEXT  = 12, 
    SPI_CR1_CRCEN    = 13, 
    SPI_CR1_BIDIOE   = 14, 
    SPI_CR1_BIDIMODE = 15  
} SPI_CR1_te;

SPI_CR2_te

enum SPI_CR2_te

SPI_CR2 register bit positions.

Enumerator
SPI_CR2_RXDMAEN	Bit 0: Rx buffer DMA enable.
SPI_CR2_TXDMAEN	Bit 1: Tx buffer DMA enable.
SPI_CR2_SSOE	Bit 2: SS output enable (master HW-NSS mode).
SPI_CR2_FRF	Bit 4: Frame format (0 = Motorola, 1 = TI).
SPI_CR2_ERRIE	Bit 5: Error interrupt enable.
SPI_CR2_RXNEIE	Bit 6: RXNE interrupt enable.
SPI_CR2_TXEIE	Bit 7: TXE interrupt enable.

Definition at line 408 of file stm32f401re.h.

{
    SPI_CR2_RXDMAEN = 0, 
    SPI_CR2_TXDMAEN = 1, 
    SPI_CR2_SSOE    = 2, 
    SPI_CR2_FRF     = 4, 
    SPI_CR2_ERRIE   = 5, 
    SPI_CR2_RXNEIE  = 6, 
    SPI_CR2_TXEIE   = 7  
} SPI_CR2_te;

SPI_SR_te

enum SPI_SR_te

SPI_SR register bit positions.

Enumerator
SPI_SR_RXNE	Bit 0: Receive buffer not empty.
SPI_SR_TXE	Bit 1: Transmit buffer empty.
SPI_SR_CHSIDE	Bit 2: Channel side (I2S).
SPI_SR_UDR	Bit 3: Underrun flag (I2S).
SPI_SR_CRCERR	Bit 4: CRC error flag.
SPI_SR_MODF	Bit 5: Mode fault (NSS low in master mode).
SPI_SR_OVR	Bit 6: Overrun flag.
SPI_SR_BSY	Bit 7: Busy flag (transfer in progress).
SPI_SR_FRE	Bit 8: Frame format error (TI mode).

Definition at line 422 of file stm32f401re.h.

{
    SPI_SR_RXNE   = 0, 
    SPI_SR_TXE    = 1, 
    SPI_SR_CHSIDE = 2, 
    SPI_SR_UDR    = 3, 
    SPI_SR_CRCERR = 4, 
    SPI_SR_MODF   = 5, 
    SPI_SR_OVR    = 6, 
    SPI_SR_BSY    = 7, 
    SPI_SR_FRE    = 8  
} SPI_SR_te;

RCC_CFGR_te

enum RCC_CFGR_te

RCC_CFGR register bit positions.

Enumerator
RCC_CFGR_SWS	Bits 3:2: System clock switch status (read-only). 0=HSI, 1=HSE, 2=PLL.
RCC_CFGR_HPRE	Bits 7:4: AHB prescaler. Values ≤ 7 = /1; 8–11 = /2,4,8,16; 12–15 = /64,128,256,512.
RCC_CFGR_PPRE1	Bits 12:10: APB1 (low-speed) prescaler. < 4 = /1; ≥ 4 = /2,4,8,16.
RCC_CFGR_PPRE2	Bits 15:13: APB2 (high-speed) prescaler. Same encoding as PPRE1.

Definition at line 438 of file stm32f401re.h.

{
    RCC_CFGR_SWS   = 2,  
    RCC_CFGR_HPRE  = 4,  
    RCC_CFGR_PPRE1 = 10, 
    RCC_CFGR_PPRE2 = 13  
} RCC_CFGR_te;

I2C_CR1_te

enum I2C_CR1_te

I2C_CR1 register bit positions.

Enumerator
I2C_CR1_PE	Bit 0: Peripheral enable.
I2C_CR1_SMBUS	Bit 1: SMBus mode.
I2C_CR1_SMBTYPE	Bit 3: SMBus type (0 = device, 1 = host).
I2C_CR1_ENARP	Bit 4: ARP enable.
I2C_CR1_ENPEC	Bit 5: PEC enable.
I2C_CR1_ENGC	Bit 6: General call enable.
I2C_CR1_NOSTRETCH	Bit 7: Clock stretching disable (slave mode).
I2C_CR1_START	Bit 8: Start generation.
I2C_CR1_STOP	Bit 9: Stop generation.
I2C_CR1_ACK	Bit 10: Acknowledge enable.
I2C_CR1_POS	Bit 11: Acknowledge/PEC position (for 2-byte reception).
I2C_CR1_PEC	Bit 12: Packet error checking.
I2C_CR1_ALERT	Bit 13: SMBus alert.
I2C_CR1_SWRST	Bit 15: Software reset.

Definition at line 449 of file stm32f401re.h.

{
    I2C_CR1_PE        = 0,  
    I2C_CR1_SMBUS     = 1,  
    I2C_CR1_SMBTYPE   = 3,  
    I2C_CR1_ENARP     = 4,  
    I2C_CR1_ENPEC     = 5,  
    I2C_CR1_ENGC      = 6,  
    I2C_CR1_NOSTRETCH = 7,  
    I2C_CR1_START     = 8,  
    I2C_CR1_STOP      = 9,  
    I2C_CR1_ACK       = 10, 
    I2C_CR1_POS       = 11, 
    I2C_CR1_PEC       = 12, 
    I2C_CR1_ALERT     = 13, 
    I2C_CR1_SWRST     = 15  
} I2C_CR1_te;

I2C_CR2_te

enum I2C_CR2_te

I2C_CR2 register bit positions.

Enumerator
I2C_CR2_FREQ	Bits 5:0: APB1 clock frequency in MHz (e.g. 16 for 16 MHz).
I2C_CR2_ITERREN	Bit 8: Error interrupt enable.
I2C_CR2_ITEVTEN	Bit 9: Event interrupt enable.
I2C_CR2_ITBUFEN	Bit 10: Buffer interrupt enable.
I2C_CR2_DMAEN	Bit 11: DMA request enable.
I2C_CR2_LAST	Bit 12: DMA last transfer (for generating NACK on final byte).

Definition at line 470 of file stm32f401re.h.

{
    I2C_CR2_FREQ    = 0,  
    I2C_CR2_ITERREN = 8,  
    I2C_CR2_ITEVTEN = 9,  
    I2C_CR2_ITBUFEN = 10, 
    I2C_CR2_DMAEN   = 11, 
    I2C_CR2_LAST    = 12  
} I2C_CR2_te;

I2C_SR1_te

enum I2C_SR1_te

I2C_SR1 register bit positions.

Enumerator
I2C_SR1_SB	Bit 0: Start bit generated. Read SR1 to clear.
I2C_SR1_ADDR	Bit 1: Address sent/matched. Read SR1 then SR2 to clear.
I2C_SR1_BTF	Bit 2: Byte transfer finished.
I2C_SR1_ADD10	Bit 3: 10-bit header sent.
I2C_SR1_STOPF	Bit 4: Stop detection (slave mode).
I2C_SR1_RxNE	Bit 6: Data register not empty (receiver).
I2C_SR1_TxE	Bit 7: Data register empty (transmitter).
I2C_SR1_BERR	Bit 8: Bus error.
I2C_SR1_ARLO	Bit 9: Arbitration lost.
I2C_SR1_AF	Bit 10: Acknowledge failure.
I2C_SR1_OVR	Bit 11: Overrun/underrun.
I2C_SR1_PECERR	Bit 12: PEC error in reception.
I2C_SR1_TIMEOUT	Bit 14: Timeout or Tlow error.
I2C_SR1_SMBALERT	Bit 15: SMBus alert.

Definition at line 483 of file stm32f401re.h.

{
    I2C_SR1_SB       = 0,  
    I2C_SR1_ADDR     = 1,  
    I2C_SR1_BTF      = 2,  
    I2C_SR1_ADD10    = 3,  
    I2C_SR1_STOPF    = 4,  
    I2C_SR1_RxNE     = 6,  
    I2C_SR1_TxE      = 7,  
    I2C_SR1_BERR     = 8,  
    I2C_SR1_ARLO     = 9,  
    I2C_SR1_AF       = 10, 
    I2C_SR1_OVR      = 11, 
    I2C_SR1_PECERR   = 12, 
    I2C_SR1_TIMEOUT  = 14, 
    I2C_SR1_SMBALERT = 15  
} I2C_SR1_te;

I2C_SR2_te

enum I2C_SR2_te

I2C_SR2 register bit positions.

Enumerator
I2C_SR2_MSL	Bit 0: Master/slave (1 = master mode).
I2C_SR2_BUSY	Bit 1: Bus busy.
I2C_SR2_TRA	Bit 2: Transmitter/receiver (1 = transmitter).
I2C_SR2_GENCALL	Bit 4: General call address received.
I2C_SR2_SMBDEFAULT	Bit 5: SMBus device default address.
I2C_SR2_SMBHOST	Bit 6: SMBus host header.
I2C_SR2_DUALF	Bit 7: Dual flag (address matched OAR2).
I2C_SR2_PEC	Bits 15:8: Packet error checking register.

Definition at line 504 of file stm32f401re.h.

{
    I2C_SR2_MSL        = 0, 
    I2C_SR2_BUSY       = 1, 
    I2C_SR2_TRA        = 2, 
    I2C_SR2_GENCALL    = 4, 
    I2C_SR2_SMBDEFAULT = 5, 
    I2C_SR2_SMBHOST    = 6, 
    I2C_SR2_DUALF      = 7, 
    I2C_SR2_PEC        = 8  
} I2C_SR2_te;

I2C_CCR_te

enum I2C_CCR_te

I2C_CCR register bit positions.

Enumerator
I2C_CCR_CCR	Bits 11:0: Clock control value. Standard: CCR = f_PCLK1/(2×f_SCL). Fast: CCR = f_PCLK1/(25×f_SCL) with DUTY=1.
I2C_CCR_DUTY	Bit 14: Fast mode duty cycle (0 = t_low/t_high = 2, 1 = 16/9).
I2C_CCR_FS	Bit 15: I2C master mode selection (0 = standard, 1 = fast).

Definition at line 519 of file stm32f401re.h.

{
    I2C_CCR_CCR  = 0,  
    I2C_CCR_DUTY = 14, 
    I2C_CCR_FS   = 15  
} I2C_CCR_te;

I2C_OAR1_te

enum I2C_OAR1_te

I2C_OAR1 register bit positions.

Enumerator
I2C_OAR1_ADD0	Bit 0: LSB of 10-bit address.
I2C_OAR1_ADD7_1	Bits 7:1: 7-bit address or bits 7:1 of 10-bit address.
I2C_OAR1_ADD9_8	Bits 9:8: Bits 9:8 of 10-bit address.
I2C_OAR1_ADDMODE	Bit 15: Addressing mode (0 = 7-bit, 1 = 10-bit).

Definition at line 529 of file stm32f401re.h.

{
    I2C_OAR1_ADD0    = 0,  
    I2C_OAR1_ADD7_1  = 1,  
    I2C_OAR1_ADD9_8  = 8,  
    I2C_OAR1_ADDMODE = 15  
} I2C_OAR1_te;

USART_SR_te

enum USART_SR_te

USART_SR register bit positions.

Enumerator
USART_SR_PE	Bit 0: Parity error.
USART_SR_FE	Bit 1: Framing error.
USART_SR_NF	Bit 2: Noise detected.
USART_SR_ORE	Bit 3: Overrun error.
USART_SR_IDLE	Bit 4: IDLE line detected.
USART_SR_RXNE	Bit 5: Read data register not empty (data received).
USART_SR_TC	Bit 6: Transmission complete (all bits shifted out).
USART_SR_TXE	Bit 7: Transmit data register empty (ready for next byte).
USART_SR_LBD	Bit 8: LIN break detection flag.
USART_SR_CTS	Bit 9: CTS flag.

Definition at line 540 of file stm32f401re.h.

{
    USART_SR_PE   = 0, 
    USART_SR_FE   = 1, 
    USART_SR_NF   = 2, 
    USART_SR_ORE  = 3, 
    USART_SR_IDLE = 4, 
    USART_SR_RXNE = 5, 
    USART_SR_TC   = 6, 
    USART_SR_TXE  = 7, 
    USART_SR_LBD  = 8, 
    USART_SR_CTS  = 9  
} USART_SR_te;

USART_BRR_te

enum USART_BRR_te

USART_BRR register bit positions.

Enumerator
USART_BRR_DIV_FRACTION	Bits 3:0: Fractional part of USARTDIV.
USART_BRR_DIV_MANTISSA	Bits 15:4: Mantissa of USARTDIV.

Definition at line 557 of file stm32f401re.h.

{
    USART_BRR_DIV_FRACTION = 0, 
    USART_BRR_DIV_MANTISSA = 4  
} USART_BRR_te;

USART_CR1_te

enum USART_CR1_te

USART_CR1 register bit positions.

Enumerator
USART_CR1_SBK	Bit 0: Send break.
USART_CR1_RWU	Bit 1: Receiver wakeup.
USART_CR1_RE	Bit 2: Receiver enable.
USART_CR1_TE	Bit 3: Transmitter enable.
USART_CR1_IDLEIE	Bit 4: IDLE interrupt enable.
USART_CR1_RXNEIE	Bit 5: RXNE interrupt enable.
USART_CR1_TCIE	Bit 6: Transmission complete interrupt enable.
USART_CR1_TXEIE	Bit 7: TXE interrupt enable.
USART_CR1_PEIE	Bit 8: PE interrupt enable.
USART_CR1_PS	Bit 9: Parity selection (0 = even, 1 = odd).
USART_CR1_PCE	Bit 10: Parity control enable.
USART_CR1_WAKE	Bit 11: Wakeup method.
USART_CR1_M	Bit 12: Word length (0 = 8 bits, 1 = 9 bits).
USART_CR1_UE	Bit 13: USART enable.
USART_CR1_OVER8	Bit 15: Oversampling mode (0 = ×16, 1 = ×8).

Definition at line 566 of file stm32f401re.h.

{
    USART_CR1_SBK    = 0,  
    USART_CR1_RWU    = 1,  
    USART_CR1_RE     = 2,  
    USART_CR1_TE     = 3,  
    USART_CR1_IDLEIE = 4,  
    USART_CR1_RXNEIE = 5,  
    USART_CR1_TCIE   = 6,  
    USART_CR1_TXEIE  = 7,  
    USART_CR1_PEIE   = 8,  
    USART_CR1_PS     = 9,  
    USART_CR1_PCE    = 10, 
    USART_CR1_WAKE   = 11, 
    USART_CR1_M      = 12, 
    USART_CR1_UE     = 13, 
    USART_CR1_OVER8  = 15  
} USART_CR1_te;

USART_CR2_te

enum USART_CR2_te

USART_CR2 register bit positions.

Enumerator
USART_CR2_ADD	Bits 3:0: Address of the USART node.
USART_CR2_LBDL	Bit 5: LIN break detection length.
USART_CR2_LBDIE	Bit 6: LIN break detection interrupt enable.
USART_CR2_LBCL	Bit 8: Last bit clock pulse (sync mode).
USART_CR2_CPHA	Bit 9: Clock phase (sync mode).
USART_CR2_CPOL	Bit 10: Clock polarity (sync mode).
USART_CR2_CLKEN	Bit 11: Clock enable (sync mode).
USART_CR2_STOP	Bits 13:12: Stop bits (0=1, 1=0.5, 2=2, 3=1.5).
USART_CR2_LINEN	Bit 14: LIN mode enable.

Definition at line 588 of file stm32f401re.h.

{
    USART_CR2_ADD   = 0,  
    USART_CR2_LBDL  = 5,  
    USART_CR2_LBDIE = 6,  
    USART_CR2_LBCL  = 8,  
    USART_CR2_CPHA  = 9,  
    USART_CR2_CPOL  = 10, 
    USART_CR2_CLKEN = 11, 
    USART_CR2_STOP  = 12, 
    USART_CR2_LINEN = 14  
} USART_CR2_te;

USART_CR3_te

enum USART_CR3_te

USART_CR3 register bit positions.

Enumerator
USART_CR3_EIE	Bit 0: Error interrupt enable.
USART_CR3_IREN	Bit 1: IrDA mode enable.
USART_CR3_IRLP	Bit 2: IrDA low-power.
USART_CR3_HDSEL	Bit 3: Half-duplex selection.
USART_CR3_NACK	Bit 4: Smartcard NACK enable.
USART_CR3_SCEN	Bit 5: Smartcard mode enable.
USART_CR3_DMAR	Bit 6: DMA enable receiver.
USART_CR3_DMAT	Bit 7: DMA enable transmitter.
USART_CR3_RTSE	Bit 8: RTS enable.
USART_CR3_CTSE	Bit 9: CTS enable.
USART_CR3_CTSIE	Bit 10: CTS interrupt enable.
USART_CR3_ONEBIT	Bit 11: One sample bit method enable (0 = 3-sample, 1 = 1-sample).

Definition at line 604 of file stm32f401re.h.

{
    USART_CR3_EIE    = 0,  
    USART_CR3_IREN   = 1,  
    USART_CR3_IRLP   = 2,  
    USART_CR3_HDSEL  = 3,  
    USART_CR3_NACK   = 4,  
    USART_CR3_SCEN   = 5,  
    USART_CR3_DMAR   = 6,  
    USART_CR3_DMAT   = 7,  
    USART_CR3_RTSE   = 8,  
    USART_CR3_CTSE   = 9,  
    USART_CR3_CTSIE  = 10, 
    USART_CR3_ONEBIT = 11  
} USART_CR3_te;

RCC_AHB1ENR_te

enum RCC_AHB1ENR_te

RCC_AHB1ENR register bit positions.

Enumerator
RCC_AHB1ENR_GPIOAEN	Bit 0: GPIOA clock enable.
RCC_AHB1ENR_GPIOBEN	Bit 1: GPIOB clock enable.
RCC_AHB1ENR_GPIOCEN	Bit 2: GPIOC clock enable.
RCC_AHB1ENR_GPIODEN	Bit 3: GPIOD clock enable.
RCC_AHB1ENR_GPIOEEN	Bit 4: GPIOE clock enable.
RCC_AHB1ENR_GPIOHEN	Bit 7: GPIOH clock enable.
RCC_AHB1ENR_CRCEN	Bit 12: CRC clock enable.
RCC_AHB1ENR_DMA1EN	Bit 21: DMA1 clock enable.
RCC_AHB1ENR_DMA2EN	Bit 22: DMA2 clock enable.

Definition at line 623 of file stm32f401re.h.

{
    RCC_AHB1ENR_GPIOAEN = 0,  
    RCC_AHB1ENR_GPIOBEN = 1,  
    RCC_AHB1ENR_GPIOCEN = 2,  
    RCC_AHB1ENR_GPIODEN = 3,  
    RCC_AHB1ENR_GPIOEEN = 4,  
    RCC_AHB1ENR_GPIOHEN = 7,  
    RCC_AHB1ENR_CRCEN   = 12, 
    RCC_AHB1ENR_DMA1EN  = 21, 
    RCC_AHB1ENR_DMA2EN  = 22  
} RCC_AHB1ENR_te;

RCC_AHB1RSTR_te

enum RCC_AHB1RSTR_te

RCC_AHB1RSTR register bit positions.

Enumerator
RCC_AHB1RSTR_GPIOARST	Bit 0: GPIOA reset.
RCC_AHB1RSTR_GPIOBRST	Bit 1: GPIOB reset.
RCC_AHB1RSTR_GPIOCRST	Bit 2: GPIOC reset.
RCC_AHB1RSTR_GPIODRST	Bit 3: GPIOD reset.
RCC_AHB1RSTR_GPIOERST	Bit 4: GPIOE reset.
RCC_AHB1RSTR_GPIOHRST	Bit 7: GPIOH reset.
RCC_AHB1RSTR_CRCRST	Bit 12: CRC reset.
RCC_AHB1RSTR_DMA1RST	Bit 21: DMA1 reset.
RCC_AHB1RSTR_DMA2RST	Bit 22: DMA2 reset.

Definition at line 639 of file stm32f401re.h.

{
    RCC_AHB1RSTR_GPIOARST = 0,  
    RCC_AHB1RSTR_GPIOBRST = 1,  
    RCC_AHB1RSTR_GPIOCRST = 2,  
    RCC_AHB1RSTR_GPIODRST = 3,  
    RCC_AHB1RSTR_GPIOERST = 4,  
    RCC_AHB1RSTR_GPIOHRST = 7,  
    RCC_AHB1RSTR_CRCRST   = 12, 
    RCC_AHB1RSTR_DMA1RST  = 21, 
    RCC_AHB1RSTR_DMA2RST  = 22  
} RCC_AHB1RSTR_te;

RCC_APB1ENR_te

enum RCC_APB1ENR_te

RCC_APB1ENR register bit positions.

Enumerator
RCC_APB1ENR_TIM2EN	Bit 0: TIM2 clock enable.
RCC_APB1ENR_TIM3EN	Bit 1: TIM3 clock enable.
RCC_APB1ENR_TIM4EN	Bit 2: TIM4 clock enable.
RCC_APB1ENR_TIM5EN	Bit 3: TIM5 clock enable.
RCC_APB1ENR_WWDGEN	Bit 11: WWDG clock enable.
RCC_APB1ENR_SPI2EN	Bit 14: SPI2 clock enable.
RCC_APB1ENR_SPI3EN	Bit 15: SPI3 clock enable.
RCC_APB1ENR_USART2EN	Bit 17: USART2 clock enable.
RCC_APB1ENR_I2C1EN	Bit 21: I2C1 clock enable.
RCC_APB1ENR_I2C2EN	Bit 22: I2C2 clock enable.
RCC_APB1ENR_I2C3EN	Bit 23: I2C3 clock enable.
RCC_APB1ENR_PWREN	Bit 28: Power interface clock enable.

Definition at line 655 of file stm32f401re.h.

{
    RCC_APB1ENR_TIM2EN   = 0,  
    RCC_APB1ENR_TIM3EN   = 1,  
    RCC_APB1ENR_TIM4EN   = 2,  
    RCC_APB1ENR_TIM5EN   = 3,  
    RCC_APB1ENR_WWDGEN   = 11, 
    RCC_APB1ENR_SPI2EN   = 14, 
    RCC_APB1ENR_SPI3EN   = 15, 
    RCC_APB1ENR_USART2EN = 17, 
    RCC_APB1ENR_I2C1EN   = 21, 
    RCC_APB1ENR_I2C2EN   = 22, 
    RCC_APB1ENR_I2C3EN   = 23, 
    RCC_APB1ENR_PWREN    = 28  
} RCC_APB1ENR_te;

RCC_APB1RSTR_te

enum RCC_APB1RSTR_te

RCC_APB1RSTR register bit positions.

Enumerator
RCC_APB1RSTR_TIM2RST	Bit 0: TIM2 reset.
RCC_APB1RSTR_TIM3RST	Bit 1: TIM3 reset.
RCC_APB1RSTR_TIM4RST	Bit 2: TIM4 reset.
RCC_APB1RSTR_TIM5RST	Bit 3: TIM5 reset.
RCC_APB1RSTR_WWDGRST	Bit 11: WWDG reset.
RCC_APB1RSTR_SPI2RST	Bit 14: SPI2 reset.
RCC_APB1RSTR_SPI3RST	Bit 15: SPI3 reset.
RCC_APB1RSTR_USART2RST	Bit 17: USART2 reset.
RCC_APB1RSTR_I2C1RST	Bit 21: I2C1 reset.
RCC_APB1RSTR_I2C2RST	Bit 22: I2C2 reset.
RCC_APB1RSTR_I2C3RST	Bit 23: I2C3 reset.
RCC_APB1RSTR_PWRRST	Bit 28: Power interface reset.

Definition at line 674 of file stm32f401re.h.

{
    RCC_APB1RSTR_TIM2RST   = 0,  
    RCC_APB1RSTR_TIM3RST   = 1,  
    RCC_APB1RSTR_TIM4RST   = 2,  
    RCC_APB1RSTR_TIM5RST   = 3,  
    RCC_APB1RSTR_WWDGRST   = 11, 
    RCC_APB1RSTR_SPI2RST   = 14, 
    RCC_APB1RSTR_SPI3RST   = 15, 
    RCC_APB1RSTR_USART2RST = 17, 
    RCC_APB1RSTR_I2C1RST   = 21, 
    RCC_APB1RSTR_I2C2RST   = 22, 
    RCC_APB1RSTR_I2C3RST   = 23, 
    RCC_APB1RSTR_PWRRST    = 28  
} RCC_APB1RSTR_te;

RCC_APB2ENR_te

enum RCC_APB2ENR_te

RCC_APB2ENR register bit positions.

Enumerator
RCC_APB2ENR_TIM1EN	Bit 0: TIM1 clock enable.
RCC_APB2ENR_USART1EN	Bit 4: USART1 clock enable.
RCC_APB2ENR_USART6EN	Bit 5: USART6 clock enable.
RCC_APB2ENR_ADC1EN	Bit 8: ADC1 clock enable.
RCC_APB2ENR_SDIOEN	Bit 11: SDIO clock enable.
RCC_APB2ENR_SPI1EN	Bit 12: SPI1 clock enable.
RCC_APB2ENR_SPI4EN	Bit 13: SPI4 clock enable.
RCC_APB2ENR_SYSCFGEN	Bit 14: SYSCFG clock enable.
RCC_APB2ENR_TIM9EN	Bit 16: TIM9 clock enable.
RCC_APB2ENR_TIM10EN	Bit 17: TIM10 clock enable.
RCC_APB2ENR_TIM11EN	Bit 18: TIM11 clock enable.

Definition at line 693 of file stm32f401re.h.

{
    RCC_APB2ENR_TIM1EN   = 0,  
    RCC_APB2ENR_USART1EN = 4,  
    RCC_APB2ENR_USART6EN = 5,  
    RCC_APB2ENR_ADC1EN   = 8,  
    RCC_APB2ENR_SDIOEN   = 11, 
    RCC_APB2ENR_SPI1EN   = 12, 
    RCC_APB2ENR_SPI4EN   = 13, 
    RCC_APB2ENR_SYSCFGEN = 14, 
    RCC_APB2ENR_TIM9EN   = 16, 
    RCC_APB2ENR_TIM10EN  = 17, 
    RCC_APB2ENR_TIM11EN  = 18  
} RCC_APB2ENR_te;

RCC_APB2RSTR_te

enum RCC_APB2RSTR_te

RCC_APB2RSTR register bit positions.

Enumerator
RCC_APB2RSTR_TIM1RST	Bit 0: TIM1 reset.
RCC_APB2RSTR_USART1RST	Bit 4: USART1 reset.
RCC_APB2RSTR_USART6RST	Bit 5: USART6 reset.
RCC_APB2RSTR_ADC1RST	Bit 8: ADC1 reset.
RCC_APB2RSTR_SDIORST	Bit 11: SDIO reset.
RCC_APB2RSTR_SPI1RST	Bit 12: SPI1 reset.
RCC_APB2RSTR_SPI4RST	Bit 13: SPI4 reset.
RCC_APB2RSTR_SYSCFGRST	Bit 14: SYSCFG reset.
RCC_APB2RSTR_TIM9RST	Bit 16: TIM9 reset.
RCC_APB2RSTR_TIM10RST	Bit 17: TIM10 reset.
RCC_APB2RSTR_TIM11RST	Bit 18: TIM11 reset.

Definition at line 711 of file stm32f401re.h.

{
    RCC_APB2RSTR_TIM1RST   = 0,  
    RCC_APB2RSTR_USART1RST = 4,  
    RCC_APB2RSTR_USART6RST = 5,  
    RCC_APB2RSTR_ADC1RST   = 8,  
    RCC_APB2RSTR_SDIORST   = 11, 
    RCC_APB2RSTR_SPI1RST   = 12, 
    RCC_APB2RSTR_SPI4RST   = 13, 
    RCC_APB2RSTR_SYSCFGRST = 14, 
    RCC_APB2RSTR_TIM9RST   = 16, 
    RCC_APB2RSTR_TIM10RST  = 17, 
    RCC_APB2RSTR_TIM11RST  = 18  
} RCC_APB2RSTR_te;