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arm_cortex_m4_nvic.c
Go to the documentation of this file.
1
11
12#include "arm_cortex_m4_nvic.h"
13#include "arm_cortex_m4.h"
14#include "common.h"
15#include "stm32f401re.h"
16
21
23void nvic_set_interrupt(IRQn_te interrupt_line, EN_STATUS_te en_status) {
24 if(en_status == ENABLE) {
25 if(interrupt_line < 32)
26 NVIC_ISER->NVIC_ISER_[0] |= 1u << interrupt_line;
27 else if(interrupt_line < 64)
28 NVIC_ISER->NVIC_ISER_[1] |= 1u << (interrupt_line % 32);
29 else if(interrupt_line < 96)
30 NVIC_ISER->NVIC_ISER_[2] |= 1u << (interrupt_line % 32);
31 else if(interrupt_line < 128)
32 NVIC_ISER->NVIC_ISER_[3] |= 1u << (interrupt_line % 32);
33 else if(interrupt_line < 160)
34 NVIC_ISER->NVIC_ISER_[3] |= 1u << (interrupt_line % 32);
35 else if(interrupt_line < 192)
36 NVIC_ISER->NVIC_ISER_[4] |= 1u << (interrupt_line % 32);
37 else if(interrupt_line < 224)
38 NVIC_ISER->NVIC_ISER_[5] |= 1u << (interrupt_line % 32);
39 else if(interrupt_line < 256)
40 NVIC_ISER->NVIC_ISER_[6] |= 1u << (interrupt_line % 32);
41 else if(interrupt_line < 288)
42 NVIC_ISER->NVIC_ISER_[7] |= 1u << (interrupt_line % 32);
43 }
44 else if(en_status == DISABLE) {
45 if(interrupt_line < 32)
46 NVIC_ICER->NVIC_ICER_[0] |= 1u << interrupt_line;
47 else if(interrupt_line < 64)
48 NVIC_ICER->NVIC_ICER_[1] |= 1u << (interrupt_line % 32);
49 else if(interrupt_line < 96)
50 NVIC_ICER->NVIC_ICER_[2] |= 1u << (interrupt_line % 32);
51 else if(interrupt_line < 128)
52 NVIC_ICER->NVIC_ICER_[3] |= 1u << (interrupt_line % 32);
53 else if(interrupt_line < 160)
54 NVIC_ICER->NVIC_ICER_[3] |= 1u << (interrupt_line % 32);
55 else if(interrupt_line < 192)
56 NVIC_ICER->NVIC_ICER_[4] |= 1u << (interrupt_line % 32);
57 else if(interrupt_line < 224)
58 NVIC_ICER->NVIC_ICER_[5] |= 1u << (interrupt_line % 32);
59 else if(interrupt_line < 256)
60 NVIC_ICER->NVIC_ICER_[6] |= 1u << (interrupt_line % 32);
61 else if(interrupt_line < 288)
62 NVIC_ICER->NVIC_ICER_[7] |= 1u << (interrupt_line % 32);
63 }
64}
65
arm_cortex_m4.h
Register definitions and bit position enumerations for the Arm Cortex-M4 core peripherals.
arm_cortex_m4_nvic.h
Arm Cortex-M4 NVIC driver public API.
common.h
Common utility module public API.
EN_STATUS_te
EN_STATUS_te
Represents an enabled or disabled state.
Definition common.h:95
ENABLE
@ ENABLE
Definition common.h:100
DISABLE
@ DISABLE
Definition common.h:97
nvic_set_interrupt
void nvic_set_interrupt(IRQn_te interrupt_line, EN_STATUS_te en_status)
Enables or disables an interrupt line in the NVIC.
Definition arm_cortex_m4_nvic.c:23
IRQn_te
IRQn_te
IRQ numbers in the STM32F401RE Cortex-M4 vector table.
Definition stm32f401re.h:772
stm32f401re.h
STM32F401RE MCU-specific peripheral register definitions and bit position enumerations.