Cortex-M4 NVIC API

Public API for enabling and disabling NVIC interrupt lines. More...

Collaboration diagram for Cortex-M4 NVIC API:

Functions
void	nvic_set_interrupt (IRQn_te interrupt_line, EN_STATUS_te en_status)
	Enables or disables an interrupt line in the NVIC.

Detailed Description

Public API for enabling and disabling NVIC interrupt lines.

Function Documentation

nvic_set_interrupt()

void nvic_set_interrupt	(	IRQn_te	interrupt_line,
		EN_STATUS_te	en_status )

Enables or disables an interrupt line in the NVIC.

Writes to the appropriate NVIC_ISER register bit to enable the interrupt, or to the NVIC_ICER register bit to disable it. The correct register word is selected automatically based on the interrupt line number.

Supports interrupt lines 0–287 (register words 0–7).

Parameters

[in]	interrupt_line	The interrupt line number to configure (IRQn_te).
[in]	en_status	ENABLE to enable the interrupt line, DISABLE to disable it.

Note

Writing 0 to ISER or ICER bits has no effect; only setting bits takes action, so no read-modify-write is required.

See also

nvic_set_interrupt

Definition at line 23 of file arm_cortex_m4_nvic.c.

                                                                        {
    if(en_status == ENABLE) {
        if(interrupt_line < 32)
            NVIC_ISER->NVIC_ISER_[0] |= 1u << interrupt_line;
        else if(interrupt_line < 64)
            NVIC_ISER->NVIC_ISER_[1] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 96)
            NVIC_ISER->NVIC_ISER_[2] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 128)
            NVIC_ISER->NVIC_ISER_[3] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 160)
            NVIC_ISER->NVIC_ISER_[3] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 192)
            NVIC_ISER->NVIC_ISER_[4] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 224)
            NVIC_ISER->NVIC_ISER_[5] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 256)
            NVIC_ISER->NVIC_ISER_[6] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 288)
            NVIC_ISER->NVIC_ISER_[7] |= 1u << (interrupt_line % 32);
    }
    else if(en_status == DISABLE) {
        if(interrupt_line < 32)
            NVIC_ICER->NVIC_ICER_[0] |= 1u << interrupt_line;
        else if(interrupt_line < 64)
            NVIC_ICER->NVIC_ICER_[1] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 96)
            NVIC_ICER->NVIC_ICER_[2] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 128)
            NVIC_ICER->NVIC_ICER_[3] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 160)
            NVIC_ICER->NVIC_ICER_[3] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 192)
            NVIC_ICER->NVIC_ICER_[4] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 224)
            NVIC_ICER->NVIC_ICER_[5] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 256)
            NVIC_ICER->NVIC_ICER_[6] |= 1u << (interrupt_line % 32);
        else if(interrupt_line < 288)
            NVIC_ICER->NVIC_ICER_[7] |= 1u << (interrupt_line % 32);
    }
}

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