GPS Device
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RCC Public APIs

Functions

uint32_t rcc_get_sysclk (void)
 Returns the current system clock frequency in Hz.
uint32_t rcc_get_ahb_clk (void)
 Returns the current AHB bus clock frequency in Hz.
uint32_t rcc_get_apb1_clk (void)
 Returns the current APB1 peripheral bus clock frequency in Hz.
uint32_t rcc_get_apb2_clk (void)
 Returns the current APB2 peripheral bus clock frequency in Hz.
void rcc_set_pclk_ahb1 (RCC_AHB1ENR_te periph_position, EN_STATUS_te en_status)
 Enables or disables the peripheral clock for an AHB1 peripheral.
void rcc_set_pclk_apb1 (RCC_APB1ENR_te periph_position, EN_STATUS_te en_status)
 Enables or disables the peripheral clock for an APB1 peripheral.
void rcc_set_pclk_apb2 (RCC_APB2ENR_te periph_position, EN_STATUS_te en_status)
 Enables or disables the peripheral clock for an APB2 peripheral.
void rcc_reset_periph_ahb1 (RCC_AHB1RSTR_te periph_position)
 Resets an AHB1 peripheral via RCC_AHB1RSTR.
void rcc_reset_periph_apb1 (RCC_APB1RSTR_te periph_position)
 Resets an APB1 peripheral via RCC_APB1RSTR.
void rcc_reset_periph_apb2 (RCC_APB2RSTR_te periph_position)
 Resets an APB2 peripheral via RCC_APB2RSTR.
void rcc_reset_bkpd (void)
 Resets the backup domain.

Detailed Description

Function Documentation

◆ rcc_get_sysclk()

uint32_t rcc_get_sysclk ( void )

Returns the current system clock frequency in Hz.

See also
rcc_get_sysclk

Definition at line 21 of file stm32f401re_rcc.c.

21 {
22 uint8_t rcc_cfgr_sws = ((RCC->RCC_CFGR >> RCC_CFGR_SWS) & 0x3);
23
24 switch(rcc_cfgr_sws) {
25 case 0:
26 return 16000000; // HSI
27 case 1:
28 return 8000000; // HSE
29 /* case 2: PLL — not yet implemented */
30 }
31
32 return 0;
33}
RCC
#define RCC
Definition stm32f401re.h:734
RCC_CFGR_SWS
@ RCC_CFGR_SWS
Definition stm32f401re.h:440
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◆ rcc_get_ahb_clk()

uint32_t rcc_get_ahb_clk ( void )

Returns the current AHB bus clock frequency in Hz.

See also
rcc_get_ahb_clk

Definition at line 36 of file stm32f401re_rcc.c.

36 {
37 uint32_t system_clock = rcc_get_sysclk();
38 uint8_t rcc_cfgr_hpre = ((RCC->RCC_CFGR >> RCC_CFGR_HPRE) & 0xF);
39 uint16_t ahb_division_factor;
40
41 if(rcc_cfgr_hpre <= 7) {
42 ahb_division_factor = 1;
43 }
44 else if(rcc_cfgr_hpre <= 11) {
45 ahb_division_factor = 0x1 << (rcc_cfgr_hpre - 7);
46 }
47 else {
48 ahb_division_factor = 0x1 << (rcc_cfgr_hpre - 6);
49 }
50
51 return system_clock / ahb_division_factor;
52}
rcc_get_sysclk
uint32_t rcc_get_sysclk(void)
Returns the current system clock frequency in Hz.
Definition stm32f401re_rcc.c:21
RCC_CFGR_HPRE
@ RCC_CFGR_HPRE
Definition stm32f401re.h:441
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◆ rcc_get_apb1_clk()

uint32_t rcc_get_apb1_clk ( void )

Returns the current APB1 peripheral bus clock frequency in Hz.

Returns the current APB1 (low-speed) peripheral bus clock frequency in Hz.

See also
rcc_get_apb1_clk

Definition at line 55 of file stm32f401re_rcc.c.

55 {
56 uint32_t ahb_clock = rcc_get_ahb_clk();
57 uint8_t rcc_cfgr_ppre1 = ((RCC->RCC_CFGR >> RCC_CFGR_PPRE1) & 0x7);
58 uint8_t apb1_division_factor;
59
60 if(rcc_cfgr_ppre1 < 4) {
61 apb1_division_factor = 1;
62 }
63 else {
64 apb1_division_factor = 0x1 << (rcc_cfgr_ppre1 - 3);
65 }
66
67 return ahb_clock / apb1_division_factor;
68}
rcc_get_ahb_clk
uint32_t rcc_get_ahb_clk(void)
Returns the current AHB bus clock frequency in Hz.
Definition stm32f401re_rcc.c:36
RCC_CFGR_PPRE1
@ RCC_CFGR_PPRE1
Definition stm32f401re.h:442
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◆ rcc_get_apb2_clk()

uint32_t rcc_get_apb2_clk ( void )

Returns the current APB2 peripheral bus clock frequency in Hz.

Returns the current APB2 (high-speed) peripheral bus clock frequency in Hz.

See also
rcc_get_apb2_clk

Definition at line 71 of file stm32f401re_rcc.c.

71 {
72 uint32_t ahb_clock = rcc_get_ahb_clk();
73 uint8_t rcc_cfgr_ppre2 = ((RCC->RCC_CFGR >> RCC_CFGR_PPRE2) & 0x7);
74 uint8_t apb2_division_factor;
75
76 if(rcc_cfgr_ppre2 < 4) {
77 apb2_division_factor = 1;
78 }
79 else {
80 apb2_division_factor = 0x1 << (rcc_cfgr_ppre2 - 3);
81 }
82
83 return ahb_clock / apb2_division_factor;
84}
RCC_CFGR_PPRE2
@ RCC_CFGR_PPRE2
Definition stm32f401re.h:443
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◆ rcc_set_pclk_ahb1()

void rcc_set_pclk_ahb1 ( RCC_AHB1ENR_te periph_position,
EN_STATUS_te en_status )

Enables or disables the peripheral clock for an AHB1 peripheral.

See also
rcc_set_pclk_ahb1

Definition at line 87 of file stm32f401re_rcc.c.

87 {
88 if(en_status == ENABLE) {
89 RCC->RCC_AHB1ENR |= (0x1 << periph_position);
90 }
91 else if(en_status == DISABLE) {
92 RCC->RCC_AHB1ENR &= ~(0x1 << periph_position);
93 }
94}
ENABLE
@ ENABLE
Definition common.h:100
DISABLE
@ DISABLE
Definition common.h:97
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◆ rcc_set_pclk_apb1()

void rcc_set_pclk_apb1 ( RCC_APB1ENR_te periph_position,
EN_STATUS_te en_status )

Enables or disables the peripheral clock for an APB1 peripheral.

See also
rcc_set_pclk_apb1

Definition at line 97 of file stm32f401re_rcc.c.

97 {
98 if(en_status == ENABLE) {
99 RCC->RCC_APB1ENR |= (0x1 << periph_position);
100 }
101 else if(en_status == DISABLE) {
102 RCC->RCC_APB1ENR &= ~(0x1 << periph_position);
103 }
104}
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◆ rcc_set_pclk_apb2()

void rcc_set_pclk_apb2 ( RCC_APB2ENR_te periph_position,
EN_STATUS_te en_status )

Enables or disables the peripheral clock for an APB2 peripheral.

See also
rcc_set_pclk_apb2

Definition at line 107 of file stm32f401re_rcc.c.

107 {
108 if(en_status == ENABLE) {
109 RCC->RCC_APB2ENR |= (0x1 << periph_position);
110 }
111 else if(en_status == DISABLE) {
112 RCC->RCC_APB2ENR &= ~(0x1 << periph_position);
113 }
114}
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◆ rcc_reset_periph_ahb1()

void rcc_reset_periph_ahb1 ( RCC_AHB1RSTR_te periph_position)

Resets an AHB1 peripheral via RCC_AHB1RSTR.

See also
rcc_reset_periph_ahb1

Definition at line 117 of file stm32f401re_rcc.c.

117 {
118 RCC->RCC_AHB1RSTR |= (0x1 << periph_position);
119 RCC->RCC_AHB1RSTR &= ~(0x1 << periph_position);
120}
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◆ rcc_reset_periph_apb1()

void rcc_reset_periph_apb1 ( RCC_APB1RSTR_te periph_position)

Resets an APB1 peripheral via RCC_APB1RSTR.

See also
rcc_reset_periph_apb1

Definition at line 123 of file stm32f401re_rcc.c.

123 {
124 RCC->RCC_APB1RSTR |= (0x1 << periph_position);
125 RCC->RCC_APB1RSTR &= ~(0x1 << periph_position);
126}
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◆ rcc_reset_periph_apb2()

void rcc_reset_periph_apb2 ( RCC_APB2RSTR_te periph_position)

Resets an APB2 peripheral via RCC_APB2RSTR.

See also
rcc_reset_periph_apb2

Definition at line 129 of file stm32f401re_rcc.c.

129 {
130 RCC->RCC_APB2RSTR |= (0x1 << periph_position);
131 RCC->RCC_APB2RSTR &= ~(0x1 << periph_position);
132}
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◆ rcc_reset_bkpd()

void rcc_reset_bkpd ( void )

Resets the backup domain.

Resets the backup domain (RTC, backup registers, backup SRAM).

See also
rcc_reset_bkpd

Definition at line 135 of file stm32f401re_rcc.c.

135 {
136 RCC->RCC_BDCR |= (0x1 << RCC_BDCR_BDRST);
137 RCC->RCC_BDCR &= ~(0x1 << RCC_BDCR_BDRST);
138}
RCC_BDCR_BDRST
@ RCC_BDCR_BDRST
Definition stm32f401re.h:318