Configuration enumerations and structures for the SPI driver. More...

Collaboration diagram for SPI Types:

Classes
struct	SPI_CFG_ts
	Configuration structure for initializing an SPI peripheral. More...

Enumerations
enum	SPI_MODE_te { SPI_MODE_SLAVE , SPI_MODE_MASTER }
	SPI operating mode. More...
enum	SPI_DATA_FRAME_FORMAT_te { SPI_DATA_FRAME_FORMATE_8_BIT , SPI_DATA_FRAME_FORMAT_16_BIT }
	SPI data frame size. More...
enum	SPI_CLOCK_POLARITY_te { SPI_CLOCK_POLARITY_0_IDLE , SPI_CLOCK_POLARITY_1_IDLE }
	SPI clock polarity (CPOL). More...
enum	SPI_CLOCK_PHASE_te { SPI_CLOCK_PHASE_FIRST_TRANSITION , SPI_CLOCK_PHASE_SECOND_TRANSITION }
	SPI clock phase (CPHA). More...
enum	SPI_BIT_FIRST_te { SPI_BIT_FIRST_MSB , SPI_BIT_FIRST_LSB }
	SPI frame bit order. More...
enum	SPI_SLAVE_SELECT_MODE_te { SPI_SLAVE_SELECT_MODE_HW , SPI_SLAVE_SELECT_MODE_SW }
	SPI slave select (NSS) management mode. More...
enum	SPI_MASTER_SCLK_SPEED_te { SPI_MASTER_SCLK_SPEED_PCLK_DIV_2 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_4 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_8 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_16 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_32 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_64 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_128 , SPI_MASTER_SCLK_SPEED_PCLK_DIV_256 }
	SPI master clock speed as a division of the peripheral clock (PCLK). More...

Detailed Description

Configuration enumerations and structures for the SPI driver.

Enumeration Type Documentation

◆ SPI_MODE_te

enum SPI_MODE_te

SPI operating mode.

Enumerator
SPI_MODE_SLAVE	Slave mode: SCLK is driven by the external master.
SPI_MODE_MASTER	Master mode: SCLK is generated by this peripheral.

Definition at line 55 of file stm32f401re_spi.h.

             {
    SPI_MODE_SLAVE,  
    SPI_MODE_MASTER  
} SPI_MODE_te;

◆ SPI_DATA_FRAME_FORMAT_te

enum SPI_DATA_FRAME_FORMAT_te

SPI data frame size.

Note: The enumerator name SPI_DATA_FRAME_FORMATE_8_BIT contains a typo ("FORMATE") carried from the original implementation.

Enumerator
SPI_DATA_FRAME_FORMATE_8_BIT	8-bit data frame.
SPI_DATA_FRAME_FORMAT_16_BIT	16-bit data frame.

Definition at line 66 of file stm32f401re_spi.h.

             {
    SPI_DATA_FRAME_FORMATE_8_BIT,  
    SPI_DATA_FRAME_FORMAT_16_BIT   
} SPI_DATA_FRAME_FORMAT_te;

◆ SPI_CLOCK_POLARITY_te

enum SPI_CLOCK_POLARITY_te

SPI clock polarity (CPOL).

Determines the idle state of the SCLK line between transfers.

Enumerator
SPI_CLOCK_POLARITY_0_IDLE	CPOL = 0: SCLK is LOW when idle.
SPI_CLOCK_POLARITY_1_IDLE	CPOL = 1: SCLK is HIGH when idle.

Definition at line 77 of file stm32f401re_spi.h.

             {
    SPI_CLOCK_POLARITY_0_IDLE, 
    SPI_CLOCK_POLARITY_1_IDLE  
} SPI_CLOCK_POLARITY_te;

◆ SPI_CLOCK_PHASE_te

enum SPI_CLOCK_PHASE_te

SPI clock phase (CPHA).

Determines which clock edge is used to sample and drive data.

Enumerator
SPI_CLOCK_PHASE_FIRST_TRANSITION	CPHA = 0: data captured on the first clock edge.
SPI_CLOCK_PHASE_SECOND_TRANSITION	CPHA = 1: data captured on the second clock edge.

Definition at line 88 of file stm32f401re_spi.h.

             {
    SPI_CLOCK_PHASE_FIRST_TRANSITION,  
    SPI_CLOCK_PHASE_SECOND_TRANSITION  
} SPI_CLOCK_PHASE_te;

◆ SPI_BIT_FIRST_te

enum SPI_BIT_FIRST_te

SPI frame bit order.

Enumerator
SPI_BIT_FIRST_MSB	MSB transmitted first (standard).
SPI_BIT_FIRST_LSB	LSB transmitted first.

Definition at line 96 of file stm32f401re_spi.h.

             {
    SPI_BIT_FIRST_MSB, 
    SPI_BIT_FIRST_LSB  
} SPI_BIT_FIRST_te;

◆ SPI_SLAVE_SELECT_MODE_te

enum SPI_SLAVE_SELECT_MODE_te

SPI slave select (NSS) management mode.

Enumerator
SPI_SLAVE_SELECT_MODE_HW	Hardware NSS: managed automatically by the peripheral.
SPI_SLAVE_SELECT_MODE_SW	Software NSS: managed manually by the application via GPIO.

Definition at line 104 of file stm32f401re_spi.h.

             {
    SPI_SLAVE_SELECT_MODE_HW, 
    SPI_SLAVE_SELECT_MODE_SW  
} SPI_SLAVE_SELECT_MODE_te;

◆ SPI_MASTER_SCLK_SPEED_te

enum SPI_MASTER_SCLK_SPEED_te

SPI master clock speed as a division of the peripheral clock (PCLK).

Only relevant in master mode (SPI_MODE_MASTER). The actual SCK frequency is PCLK / divisor, where PCLK is APB2 for SPI1/SPI4 and APB1 for SPI2/SPI3.

Enumerator
SPI_MASTER_SCLK_SPEED_PCLK_DIV_2	SCK = PCLK / 2.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_4	SCK = PCLK / 4.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_8	SCK = PCLK / 8.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_16	SCK = PCLK / 16.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_32	SCK = PCLK / 32.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_64	SCK = PCLK / 64.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_128	SCK = PCLK / 128.
SPI_MASTER_SCLK_SPEED_PCLK_DIV_256	SCK = PCLK / 256.

Definition at line 117 of file stm32f401re_spi.h.

             {
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_2,   
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_4,   
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_8,   
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_16,  
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_32,  
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_64,  
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_128, 
    SPI_MASTER_SCLK_SPEED_PCLK_DIV_256  
} SPI_MASTER_SCLK_SPEED_te;

Classes

Enumerations